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Disable Replacement Update Bit

IP.com Disclosure Number: IPCOM000040271D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+6]

Abstract

This invention is a mechanism to mitigate the impact of short, asynchronous system processes on cache performance by modifying the maintenance of replacement status in the cache. In many systems, the relatively long running processes (e.g., large batch jobs, database subsystems, transaction processing systems) are interspersed with short asynchronous system transient processes (e.g., first level interrupt handlers). Transient processes start at the same place each time they are invoked and run to completion while the long running processes "pick up where they left off" when the transient processes complete.

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Disable Replacement Update Bit

This invention is a mechanism to mitigate the impact of short, asynchronous system processes on cache performance by modifying the maintenance of replacement status in the cache. In many systems, the relatively long running processes (e.g., large batch jobs, database subsystems, transaction processing systems) are interspersed with short asynchronous system transient processes (e.g., first level interrupt handlers). Transient processes start at the same place each time they are invoked and run to completion while the long running processes "pick up where they left off" when the transient processes complete. The transient processes can degrade the performance of the longer running processes by changing the cache contents, that is, by replacing lines that "belong" to the long running processes with lines associated with the transient process. The transient processes, however, typically have very small working sets. Such a process can run with good performance using only a part of the large caches that are typical of current high-end commercial processors. The organization of these large caches is such that once a line in a given congruence class is used by a transient process, it is unlikely to be used again before aging out of the cache. This invention causes the updating of the replacement status bits in the cache to be suspended during the execution of such short duration processes. This has the effect of the transient process running in one-way set associative (a.k.a. direct mapped) cache with as many lines as there are congruence classes in the larger cache. It also has the effect of leaving both the data and the replac...