Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Fast Carry Sum Adder

IP.com Disclosure Number: IPCOM000040274D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Ouellette, MR: AUTHOR [+2]

Abstract

An improved complementary metal-oxide semiconductor (CMOS) carry sum adder (CSA) which is 35-50 percent faster than existing CSAs is described. This CSA requires no more chip area than conventional CSAs and uses two less devices. Referring to the figure, operation of the EXOR and EXNOR is essentially identical. If A0 is high and B0 is high, T5 and T6 are turned off and T4 is turned on. The input inverter's (T1 and T2) output is low, so T3 is turned off. A low is provided to the source of T4, and C1 is low. When A0 falls, T4 is turned off and T6 is turned on, driving C1 high. The delay is approximately equal to that of an inverter. When B0 falls, T5 turns on, the input inverter's output rises, turning on T3, and C1 falls. The total delay is close to that of an inverter.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Fast Carry Sum Adder

An improved complementary metal-oxide semiconductor (CMOS) carry sum adder (CSA) which is 35-50 percent faster than existing CSAs is described. This CSA requires no more chip area than conventional CSAs and uses two less devices. Referring to the figure, operation of the EXOR and EXNOR is essentially identical. If A0 is high and B0 is high, T5 and T6 are turned off and T4 is turned on. The input inverter's (T1 and T2) output is low, so T3 is turned off. A low is provided to the source of T4, and C1 is low. When A0 falls, T4 is turned off and T6 is turned on, driving C1 high. The delay is approximately equal to that of an inverter. When B0 falls, T5 turns on, the input inverter's output rises, turning on T3, and C1 falls. The total delay is close to that of an inverter. When A0 rises, T6 turns off, T4 turns on, and C1 is driven high. The delay is approximately equal to that of an inverter. the EXNOR's delays are very similar to the EXOR's delays. The total sum delay is equivalent to 1.5-1.8 logic delay stages. The carry circuit is identical to state-of-the-art carry logic.

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]