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High-Level Discretionary Wiring for Wafer Scale Integration

IP.com Disclosure Number: IPCOM000040275D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Ketchan, MB: AUTHOR

Abstract

A technique for supplying element redundancy for wafers having a plurality of transistors is provided to permit wafer scale integration. The technique comprises: providing redundant element interconnections for the wafer elements; incorporating switches, control circuitry, and associated wiring in a testing means; providing at least one contact pad for each wafer element for contacting by a probe during testing; testing the wafer to identify a working element combination of elements in the wafer; and hard-wiring the identified working element combination using the provided redundant wafer element interconnections and the identified wafer elements.

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High-Level Discretionary Wiring for Wafer Scale Integration

A technique for supplying element redundancy for wafers having a plurality of transistors is provided to permit wafer scale integration. The technique comprises: providing redundant element interconnections for the wafer elements; incorporating switches, control circuitry, and associated wiring in a testing means; providing at least one contact pad for each wafer element for contacting by a probe during testing; testing the wafer to identify a working element combination of elements in the wafer; and hard-wiring the identified working element combination using the provided redundant wafer element interconnections and the identified wafer elements. According to the instant technique which is particularly useful for wafer scale integration of field effect transistors where the element size tends to be between 500 and 1000 circuits, redundant element interconnections are provided for each element in the wafer in such a manner as is known in the on-board switching arts. At least one contact pad is also provided for each element such that it may be contacted by an area array probe. A testing means which incorporates switches, control circuitry and associated wiring is then used to test the wafer and a working combination of elements in the wafer is identified in such a manner as is known in the on-board switching arts. The working combination is then hard-wired in place according to any of various techniques....