Browse Prior Art Database

Functional Simulator for Memory Devices

IP.com Disclosure Number: IPCOM000040276D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Steinberg, FR: AUTHOR

Abstract

Functional simulators are frequently used to model memory devices for a circuit design. Some functional simulators model memory devices so one can only write to the memory device and then read from it in one cycle. In many applications, designers need the ability to read from a simulated memory and then write to it in the same cycle of simulation. Fig. 1 shows that this can be accomplished using a write-before- read primitive. The model latches the input data and input address for use in the next cycle of simulation. The input write enable signal is also latched with a one-shot latch. The input read enable and read address are not latched so that the read function occurs during the cycle the read enable signal is present.

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Functional Simulator for Memory Devices

Functional simulators are frequently used to model memory devices for a circuit design. Some functional simulators model memory devices so one can only write to the memory device and then read from it in one cycle. In many applications, designers need the ability to read from a simulated memory and then write to it in the same cycle of simulation. Fig. 1 shows that this can be accomplished using a write-before- read primitive. The model latches the input data and input address for use in the next cycle of simulation. The input write enable signal is also latched with a one-shot latch. The input read enable and read address are not latched so that the read function occurs during the cycle the read enable signal is present. Since the input write signal

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is latched, the write function will be executed a cycle after the write enable signal is present on the model's input line. A timing diagram of the model's input and output lines is provided in Fig. 2. This system, in effect, delays the write execution one cycle to make the model look like it reads before it writes in the same cycle.

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