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Shallow Junction Device for Electrostatic Discharge Protection

IP.com Disclosure Number: IPCOM000040304D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Geissler, S: AUTHOR

Abstract

By means of a shallow junction, drain electric field and avalanche current is increased in a field-effect transistor, thus creating an improved electrostatic discharge protective device. Processing of a standard dymamic random-access memory array is used to make the device. Referring to the figure, a normal N+ source junction 2 is formed in silicon substrate 4. Another normal-depth N+ junction 6 is formed to connect to the shallow N-skin 8 which normally exists under first level polysilicon 10. Second-level polysilicon 12 acts as a gate for the device and is connected to source 2 and ground. Drain connection 6 is connected to polysilicon gate 10, to pad 14, and to protected device(s) PD.

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Shallow Junction Device for Electrostatic Discharge Protection

By means of a shallow junction, drain electric field and avalanche current is increased in a field-effect transistor, thus creating an improved electrostatic discharge protective device. Processing of a standard dymamic random-access memory array is used to make the device. Referring to the figure, a normal N+ source junction 2 is formed in silicon substrate 4. Another normal-depth N+ junction 6 is formed to connect to the shallow N-skin 8 which normally exists under first level polysilicon 10. Second-level polysilicon 12 acts as a gate for the device and is connected to source 2 and ground. Drain connection 6 is connected to polysilicon gate 10, to pad 14, and to protected device(s) PD. When an electrostatic discharge event occurs, a high electric field builds quickly at the edge of shallow junction 8 under overlapping polysilicon 12 and 10. Thus, avalanche occurs at relatively low voltage, and charge is leaked to ground before damage can occur to protected devices PD.

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