Browse Prior Art Database

Word Line Segmenting With Two-Dimensional Decoding

IP.com Disclosure Number: IPCOM000040306D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Sprogis, EJ: AUTHOR

Abstract

A segmented word line architecture is accomplished by decoding local word line segment pairs through a combination of a decoded global word line and control lines. Thus, access time of dynamic random- access memory is reduced by holding resistance and capacitance of local word lines low. The figure shows one segment of N segmented pairs of local word lines 2 and 2A. Global word line 4 is driven by global word line driver circuit 10. Control lines C1 and C2 are driven from control line driver circuit 8, and control lines C3 and C4 are driven by control line driver circuit 13. Circuits 8 and 13 may be imbedded within sense amplifier and bit switch circuit block 12. Circuit operation is described assuming active-low word lines.

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Word Line Segmenting With Two-Dimensional Decoding

A segmented word line architecture is accomplished by decoding local word line segment pairs through a combination of a decoded global word line and control lines. Thus, access time of dynamic random- access memory is reduced by holding resistance and capacitance of local word lines low. The figure shows one segment of N segmented pairs of local word lines 2 and 2A. Global word line 4 is driven by global word line driver circuit 10. Control lines C1 and C2 are driven from control line driver circuit 8, and control lines C3 and C4 are driven by control line driver circuit 13. Circuits 8 and 13 may be imbedded within sense amplifier and bit switch circuit block 12. Circuit operation is described assuming active-low word lines. A similar circuit is possible for active-high word lines with appropriate device type and polarity changes. In standby and in an unselected state, global word line 4 is low, thus keeping N-channel transistors T1 and T4 off, and P- channel transistors T2 and T5 on. Lines 2 and 2A are held high by T2 and T5. Control lines C1, C2, C3 and C4 may be either high or low. Line 2 is pulled low (selected) by bringing line 4 high and simultaneously setting lines C1 and C4 low and lines C2 and C3 high. This will turn on T1 and turn off T2 and T3. Line 2A remains high, since T4 and T5 stay off, and T6 holds line 2A to Vdd. Line 2 is restored high by bringing line 4 low. This turns off T1 and turns on T2,...