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Random Pattern Testability of the Control and ADDRESS Circuitry of a Two-Port Embedded Memory With or Without Feed-Forward Data-Path Connections

IP.com Disclosure Number: IPCOM000040348D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 100K

Publishing Venue

IBM

Related People

McAnney, WH: AUTHOR [+3]

Abstract

The logical structure shown in Fig. 1 contains two-port (write port and read port) memory embedded within combinational logic and is to be tested by applying random patterns to its inputs and observing the responses on its primary outputs (marked OUT1). The random pattern testability of the write address logic, the write enable logic, the read address logic, and the read enable logic must be computed. Fig. 2 shows a flowchart for this purpose. The flowchart is intended for use in conjunction with the cutting algorithm described in an article entitled "Random Pattern Testability" by J. Savir, G. S. Ditlow, and P. H. Bardell in IEEE Transactions on Computers C-33, 1, 79-90 (January 1984). Fig. 1 shows a two-port embedded memory with feed-forward connections between prelogic and postlogic.

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Random Pattern Testability of the Control and ADDRESS Circuitry of a Two-Port Embedded Memory With or Without Feed-Forward Data-Path Connections

The logical structure shown in Fig. 1 contains two-port (write port and read port) memory embedded within combinational logic and is to be tested by applying random patterns to its inputs and observing the responses on its primary outputs (marked OUT1). The random pattern testability of the write address logic, the write enable logic, the read address logic, and the read enable logic must be computed. Fig. 2 shows a flowchart for this purpose. The flowchart is intended for use in conjunction with the cutting algorithm described in an article entitled "Random Pattern Testability" by J.

Savir, G. S. Ditlow, and P. H. Bardell in IEEE Transactions on Computers C-33, 1, 79-90 (January 1984). Fig. 1 shows a two-port embedded memory with feed-forward connections between prelogic and postlogic. The lines marked D1 through D6 are groups of primary input lines driving the logics shown. When the write and read ports select the same address, a memory "write-through" occurs in which the data-in word appears on the data-out.

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Definitions Tainted Write: A memory write to an address Z is a tainted write if either 1) address Z should have been selected but was not because the fault affected the address lines, or 2) address Z should not have been selected but was because of the fault. Fuzzy Read: A fuzzy read is a memory read from an address which has not been previously read (and has had no intervening correct writes) since the most recent tainted write to the address. K and K' are the number of fuzzy reads during the test sequence under non-write-through and write-through memory operations, respectively, and may be determined by simulation of the write and read address logic or by a suitable Markov chain. Misdirected Read: A misdirected read is any read operation which accesses the wrong address. R and R' are the number of misdirected reads under non-write-through and write-through memory operations, respectively, and may be determined by simulation of the read address and read enable logic or by a suitable Markov chain. Distorted Write: A distorted write occurs if either 1) some location should have been written but was not because the fault affected the write enable line, or 2) some location should not have been written but was because the fault struck the write enable line. Warped Read: A warped read is a memory read from an address which has not been previously read (and has had no intervening correct writes) since the m...