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Extracting Single Subfields From Error Correction Codes

IP.com Disclosure Number: IPCOM000040350D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Kadela, TF: AUTHOR

Abstract

Memory systems have frequently used the idea of merging error correction bits formed on byte boundaries for the generation of error correction check bits on larger words (sometimes referred to as codes with package detection ability of dual-mode codes). To extend the coverage provided by such a scheme, bus interfaces have been proposed that have correction codes covering both the address and data fields. As the data gets closer to its destination, superfluous address bits can be discarded to accommodate smaller local busses. Protection, provided by the error correction bits, can still be maintained through the use of error correction codes (ECCs) that allow the stripping of extraneous address bits so that the data and (reduced) address are covered with minimal code regeneration.

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Extracting Single Subfields From Error Correction Codes

Memory systems have frequently used the idea of merging error correction bits formed on byte boundaries for the generation of error correction check bits on larger words (sometimes referred to as codes with package detection ability of dual-mode codes). To extend the coverage provided by such a scheme, bus interfaces have been proposed that have correction codes covering both the address and data fields. As the data gets closer to its destination, superfluous address bits can be discarded to accommodate smaller local busses. Protection, provided by the error correction bits, can still be maintained through the use of error correction codes (ECCs) that allow the stripping of extraneous address bits so that the data and (reduced) address are covered with minimal code regeneration. The following is a description of a means by which ECC covering 8 data and 22 address bits (using 7 bits of ECC) is reduced to 8 data and 11 address bits (using 6 bits of ECC). While ECC over such a small field is usually a high cost, the coding allows the need of only one inverter level to maintain correct coding of the subset at the lowest level so the price of the improved coverage is very small. The correction codes involved are a (37,30) single error correction/double error detection (SEC-DED) code reduced to a (25,19) SEC- DED code. The terminology and basic code patterns are those presented by M.
Y. Hsaio in "A Class of Optimal Minimum Odd-Weight-Column SEC-DED codes," IBM Journal of Research and Development, July 1970. Using the system of equations in the article for generation of the parity check matrix H, columns for H can be selected and arranged in any order when the maximum number of code combinations is not needed. The resulting H matrix is shown in Fig. 1. This matrix shows a choice of 30 of the 63 possible combinations covered by 7 syndrome bit...