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Data Integrity Checking Via Chip Redundancies

IP.com Disclosure Number: IPCOM000040351D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Conomos, JA: AUTHOR [+2]

Abstract

Printed circuit chip designs frequently have large function requirements which limit the space necessary for parity checking. Limiting parity checking to only the incoming busses accommodates these design needs by utilizing two identical chips to check each other for error. Because the chips are identical, no additional design is required. The concept is described in the following. Both chips parity check the incoming busses (AT bus in and ECI bus) independently of each other and all data flow going to output busses via registers and multiplexers, i.e.

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Data Integrity Checking Via Chip Redundancies

Printed circuit chip designs frequently have large function requirements which limit the space necessary for parity checking. Limiting parity checking to only the incoming busses accommodates these design needs by utilizing two identical chips to check each other for error. Because the chips are identical, no additional design is required. The concept is described in the following. Both chips parity check the incoming busses (AT bus in and ECI bus) independently of each other and all data flow going to output busses via registers and multiplexers, i.e., the following paths: microaddress bus out to random-access memory, microaddress Stack and AT bus out to multiplexer, and the I Bus out to the IPU (the multiplexer and controls that personalize instructions out of IBM System/370 instructions and ship them out to the IPU via the I Bus). Instead of periodically checking parity as the flow is going from register to register, or from register to multiplexer, etc., access is made through the flow to the input of the drivers, disregarding parity. When data is ready to send out, parity bits are generated based on the data at the input to the drivers. This is done on both chips as they are identical. The Master chip sends the parity bits over to the Slave chip. The Slave then compares the two parity bits (Slave and Master). If the parity bits are the same, no error exists. If the parity bits are not the same, then a bit was los...