Browse Prior Art Database

GPI to CMOS Logic Level Converter or RECEIVER

IP.com Disclosure Number: IPCOM000040383D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Gruver, MR: AUTHOR [+2]

Abstract

The converter makes use of CMOS with BIPOLAR in BiFET technology to convert GPI logic levels consisting of 0.0 to 0.5 volt for a down level and 1.5 to 2.2 volts for an up level to CMOS logic levels typically consisting of 0 to 5.0-volt swings. The figure, illustrating the converter, operates as follows: The input signal is applied to Q1 of the input differential pair. When node IN goes high, Q1 conducts and Q2 turns off. As Q1 turns on, node 5 falls to 2.8 volts below the power supply. Node 3 follows node 5 to 3.6 volts below the power supply. As node 3 falls, node 4 rises and node OUT falls, turning off T9. Node VREF1 is tied to a 1.05 volt reference. When node IN falls below this voltage, Q2 turns on. This causes node 5 to rise and node 3 follows node 5 to a diode below the power supply, turning T3 off and T4 on.

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GPI to CMOS Logic Level Converter or RECEIVER

The converter makes use of CMOS with BIPOLAR in BiFET technology to convert GPI logic levels consisting of 0.0 to 0.5 volt for a down level and 1.5 to
2.2 volts for an up level to CMOS logic levels typically consisting of 0 to 5.0-volt swings. The figure, illustrating the converter, operates as follows: The input signal is applied to Q1 of the input differential pair. When node IN goes high, Q1 conducts and Q2 turns off. As Q1 turns on, node 5 falls to 2.8 volts below the power supply. Node 3 follows node 5 to 3.6 volts below the power supply. As node 3 falls, node 4 rises and node OUT falls, turning off T9. Node VREF1 is tied to a 1.05 volt reference. When node IN falls below this voltage, Q2 turns on. This causes node 5 to rise and node 3 follows node 5 to a diode below the power supply, turning T3 off and T4 on. This drives node 4 low which, in turn, drives node OUT high. As node 3 rises, Q11 is off. This allows more of the current sourced by Q2B to charge the gates of T3 and T4. An interesting feature of the circuit is the arrangement of T8 and R1. As Q1 conducts current, the voltage at node 5 falls, changing the on resistance of T8. This modulates the current in Q1 which affects the voltage at node 5. If a constant resistor of 3.0K ohms were put between node 1 and ground instead of T8, the current and power in Q1 would vary linearly with input voltage; in fact, Q1 would conduct 230 mA when VIN was
1.5 V and 460 mA when VIN was 2.2 V. With this method, Q1 conducts a more constant current between the two...