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Parity Prediction for Partitioned Incremental Registers

IP.com Disclosure Number: IPCOM000040389D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Moore, CR: AUTHOR [+2]

Abstract

A technique is described whereby parity prediction is used to detect errors in the operation of incrementable registers, for use in computer systems. The concept is used where incrementable registers must be partitioned as part of the logical functions implemented and checked for errors. Different functional portions of a register are brought together in the error detection sense, resulting in parity prediction which is similar to a single register. The three portions of the instruction address registers (IARs), as shown in the figure, are partitioned registers used to hold the real address of an instruction. Instructions may either be fetched from main storage thirty-two bits at a time or from a read only storage (ROS) unit eight bits at a time.

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Parity Prediction for Partitioned Incremental Registers

A technique is described whereby parity prediction is used to detect errors in the operation of incrementable registers, for use in computer systems. The concept is used where incrementable registers must be partitioned as part of the logical functions implemented and checked for errors. Different functional portions of a register are brought together in the error detection sense, resulting in parity prediction which is similar to a single register. The three portions of the instruction address registers (IARs), as shown in the figure, are partitioned registers used to hold the real address of an instruction. Instructions may either be fetched from main storage thirty-two bits at a time or from a read only storage (ROS) unit eight bits at a time. When an address is loaded into the IAR, partition 10 is loaded immediately following branches and interrupt operation. Once loaded, the contents remain unchanged. Partition 11 is loaded in a similar manner, also incremented each time that a word of an instruction is fetched. Partition 12 is used when fetching instructions from ROS, one byte at a time, and is incremented after each byte. Carries propagate from this partition when operating in ROS mode and into partition 11. When operating from main storage, partition 12 is loaded with zeros and remains that way. The technique of predicting parity, so as to detect errors in the incrementing portion of the logic, is ac...