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Circuit for Detecting Failure of Clock Oscillator

IP.com Disclosure Number: IPCOM000040395D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Belliveau, MJ: AUTHOR [+3]

Abstract

The drawing shows a logic circuit for detecting the failure of circuits that produce a signal X(t) on a line 2. In a simple example, the signal X(t) has a symmetrical rectangular waveform that is up for the first half of each period and down for the second half. This waveform is passed along a chain of delay circuits 3, 4 and 5 in which each delays the waveform for half the period. The outputs of these circuits are successive half periods of the waveform designated X(t-D), X(t-2D) and X(t-3D). If the clock is operating properly, no more than two consecutive signals will be both up or both down at any time. A logic circuit 6 receives these signals and produces an output that signifies that the signal X(t) is stuck at a down level.

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Circuit for Detecting Failure of Clock Oscillator

The drawing shows a logic circuit for detecting the failure of circuits that produce a signal X(t) on a line 2. In a simple example, the signal X(t) has a symmetrical rectangular waveform that is up for the first half of each period and down for the second half.

This waveform is passed along a chain of delay circuits 3, 4 and 5 in which each delays the waveform for half the period. The outputs of these circuits are successive half periods of the waveform designated X(t-D), X(t-2D) and X(t-3D). If the clock is operating properly, no more than two consecutive signals will be both up or both down at any time. A logic circuit 6 receives these signals and produces an output that signifies that the signal X(t) is stuck at a down level. Logic circuit 7 detects that the signal is stuck at an up level, and logic circuit 8 detects that either of these faults have occurred. From a more general standpoint, the circuit is described by the following inequalities. D (50-2C-502) P/100 (1)

N (50+2C-502) P/(100 D) (2) D is the time delay of each block, N is the number of delay circuits, P is the period of the waveform, and C is the percent of time the waveform is up (the duty cycle). The expression 2C-502 is the absolute value of the difference between the actual duty cycle and a 50% duty cycle. In the example of the first paragraph, the duty cycle is 50% and from equation (1) the delay is half the period. If the duty cycle is made...