Browse Prior Art Database

Parallel Processing of Systems Network Architecture Finite State Machines

IP.com Disclosure Number: IPCOM000040398D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Loucks, L: AUTHOR [+4]

Abstract

Architectural specifications for Systems Network Architecture (SNA) fail to exploit the inherant parallelism of the set of finite state machines (FSMs) used in SNA. The described method comprises software that identifies global states and inputs, and processes them in parallel in order to increase performance of a SNA implementation. A SNA basic information unit (BIU) is made up of a request/-response header (RH) and a request unit (RU). In the course of its processing, a BIU has its RH checked to determine if it is in violation of some SNA protocol. The Half Session component of SNA enforces several protocols (e.g., chaining, request/response mode, send/receive mode, and bracket protocols). Each of these protocols is enforced by a FSM procedure.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 72% of the total text.

Page 1 of 1

Parallel Processing of Systems Network Architecture Finite State Machines

Architectural specifications for Systems Network Architecture (SNA) fail to exploit the inherant parallelism of the set of finite state machines (FSMs) used in SNA. The described method comprises software that identifies global states and inputs, and processes them in parallel in order to increase performance of a SNA implementation. A SNA basic information unit (BIU) is made up of a request/- response header (RH) and a request unit (RU). In the course of its processing, a BIU has its RH checked to determine if it is in violation of some SNA protocol. The Half Session component of SNA enforces several protocols (e.g., chaining, request/response mode, send/receive mode, and bracket protocols). Each of these protocols is enforced by a FSM procedure. These procedures check the bit settings in the RH corresponding to their respective protocols. In order to improve Hals Session performance, logic was designed to check RH bit settings wordwise by padding the three-byte RH with a fourth byte and using a word mask to check all protocol indicators simultaneously (in parallel). This type of check is made instead of the bitwise (serial) checks specified in the SNA architecture. By checking the RH in this manner, it is possible to identify valid combinations of RH bit settings that produce predictable state changes. In this implementation Half Session applies the parallel bit checking in combination wi...