Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

N+ Guard Rings for CMOS Technology

IP.com Disclosure Number: IPCOM000040405D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Barber, JR: AUTHOR [+3]

Abstract

This article discloses a process for forming self-aligned guard rings during n-well formation to minimize latch-up of CMOS devices. Step 1 - Thermal silicon oxide 10 is grown on substrate 12 (Fig. 1). A layer of photoresist 14 is applied on oxide 10, and the n-well pattern is lithographically defined (Fig. 2). Step 2 - The pattern in the photoresist layer 14 has been transferred to the oxide 10 with an anisotropic dry etch with a high oxide/silicon etch rate ratio. After the pattern has been delineated in the oxide layer, a high energy ion implant creates the n-well region 16 (Fig. 3). Step 3 - The photoresist is stripped and a conformal CVD (chemical vapor deposition) nitride film is deposited. The nitride film is then blanket etched in order to form nitride spacers 18 on the sidewalls of the oxide 10 (Fig. 4).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 91% of the total text.

Page 1 of 2

N+ Guard Rings for CMOS Technology

This article discloses a process for forming self-aligned guard rings during n- well formation to minimize latch-up of CMOS devices. Step 1 - Thermal silicon oxide 10 is grown on substrate 12 (Fig. 1). A layer of photoresist 14 is applied on oxide 10, and the n-well pattern is lithographically defined (Fig. 2). Step 2 - The pattern in the photoresist layer 14 has been transferred to the oxide 10 with an anisotropic dry etch with a high oxide/silicon etch rate ratio. After the pattern has been delineated in the oxide layer, a high energy ion implant creates the n-well region 16 (Fig. 3). Step 3 - The photoresist is stripped and a conformal CVD (chemical vapor deposition) nitride film is deposited. The nitride film is then blanket etched in order to form nitride spacers 18 on the sidewalls of the oxide 10 (Fig. 4).

(Image Omitted)

Step 4 - A planarizing organic film 20, such as photoresist or polyimide, is next applied, and then blanket etched with a process that has equivalent selectivities for all three film materials: oxide, nitride and polymer. Enough film thickness is removed to expose the nitride spacer 18 (Fig. 5). Step 5 - The spacer 18 is removed with an etch having high selectivity of nitride with respect to the oxide 10 and the organic layer 20. Step 6 - A blanket implantation of an n-type species is next performed to create electrical isolation regions 22 (Fig. 6). At this point, the remaining oxide layer 10 and organi...