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Method for Finding Card Nets That Contain High Electromagnetic Interference Emission Potential

IP.com Disclosure Number: IPCOM000040407D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Stys, MS: AUTHOR

Abstract

A method is described which makes it possible for the card designer to identify high electromagnetic interference (EMI) potential card nets before hardware models are measured in the EMC lab. These nets can then be specially designed to reduce EMI emissions. As a result, fewer resources are devoted to EMC lab fixwork further along in the development cycle. Data processing equipment companies may not market or sell computers, peripherals or other electronic devices that do not meet the stringent FCC (Federal Communications Commission) regulations governing EMI emissions. Numerous engineering resources must usually be devoted to reducing product EMI in the EMC lab, and any analysis of high-EMI potential nets must be done manually.

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Method for Finding Card Nets That Contain High Electromagnetic Interference Emission Potential

A method is described which makes it possible for the card designer to identify high electromagnetic interference (EMI) potential card nets before hardware models are measured in the EMC lab. These nets can then be specially designed to reduce EMI emissions. As a result, fewer resources are devoted to EMC lab fixwork further along in the development cycle. Data processing equipment companies may not market or sell computers, peripherals or other electronic devices that do not meet the stringent FCC (Federal Communications Commission) regulations governing EMI emissions. Numerous engineering resources must usually be devoted to reducing product EMI in the EMC lab, and any analysis of high-EMI potential nets must be done manually. No automated tool is currently available to help the designer identify high-EMI potential nets suring any phase of the electronic card design cycle.

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The theoretical bases of the new method is described below. Digital clock signals are almost always the predominant producers of EMI. It can be shown that the magnitude c(N) of the harmonics of a clock signal are: where A is the voltage transition amplitude D is the duty cycle

N is the harmonic number that is multiplied by the

initial fundamental frequency to get the harmonic

frequency. If T is the period corresponding to fundamental frequency fo, then for a given harmonic frequency F

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Therefore, the harmonics which are produced by a periodic signal decrease proportionately to increases in signal period T. When pulse width is kept constant and signal period increases from T to 10T, harmonics decrease in amplitude by a factor of 10, which is 20 dB. This concept is illustrated in Figs. 1A and 1B. The vertical axis depicts the number of decibels above 1 microvolt. The horizontal axis displays frequency in units of megahertz. Harmonics are generated by a 63-millivolt pulse waveform, which is directly fed into a spectrum analyzer. Fig. 1A illustrates the magnitudes of the harmonics for pulses 100 nanoseconds wide and a period of 200 nanoseconds. Fig. 1B shows the magnitudes of the harmonics for pulses 100 nanoseconds wide and a period of 2000 nanoseconds. The results indicate that the peak harmonics seen in Fig. 1B have dropped by a factor of 10, or 20 dB, compared with those at identical freq...