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Direct Loads and Stores for a Binary Floating Point Unit

IP.com Disclosure Number: IPCOM000040428D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 4 page(s) / 34K

Publishing Venue

IBM

Related People

Rodriguez, JR: AUTHOR

Abstract

This article describes a technique that provides for automatic format conversion at the execution of direct loads and stores from and to main storage in a reduced instruction set computer (RISC)-type architecture. The technique used includes the necessary means to perform automatic format conversions as is required in a binary floating point (FP) bus unit architecture supporting direct load and store instructions. The drawing illustrates the system organization for RISC architecture in block diagram form. The basic architecture defines a computational instruction set of reduced complexity. This allows the processing unit (PU) implementation to be hardwired, and by using organizational techniques, such as pipelining, instructions can complete execution in one machine cycle.

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Direct Loads and Stores for a Binary Floating Point Unit

This article describes a technique that provides for automatic format conversion at the execution of direct loads and stores from and to main storage in a reduced instruction set computer (RISC)-type architecture. The technique used includes the necessary means to perform automatic format conversions as is required in a binary floating point (FP) bus unit architecture supporting direct load and store instructions. The drawing illustrates the system organization for RISC architecture in block diagram form. The basic architecture defines a computational instruction set of reduced complexity. This allows the processing unit (PU) implementation to be hardwired, and by using organizational techniques, such as pipelining, instructions can complete execution in one machine cycle. The PU itself is defined as a word oriented fixed point processor executing the subject instruction set. FP instructions, on the other hand, cannot be expected to be executed in one instruction cycle in typical implementations. For this reason, the arithmetic unit executing FP operations has been defined as an entity separate from the PU, called a bus unit (BU). BUs are facilities that operate either asynchronously with the PU or are expected to have instruction execution time substantially greater than the "single cycle" objective of the PU architecture, as is the case with the execution of FP instructions. The BUs are attached to the PU by a processor bus (PBus), and the instructions to these components are called PBus operations. Instructions are provided that transfer data between main storage and the FP registers in the binary floating point bus unit (BFPBU). The load direct single binary FP register (FPR) instruction transfers data from one word of memory to bits 0-31 of one of the FPRs. No format conversion is made. The store direct single binary FPR instruction transfers data from bits 0-31 of one of the FPRs to one word memory. No format conversion is made. The load direct single binary FPR and convert instruction transfers data from one word of memory to one of the FPRs. The single precision value is automatically converted to double extended format and then placed into the specified register. The store direct single binary FPR and convert instruction transfers data from one of the FPRs to one word of memory. The double extended data word is automatically converted to single precision. The exponent is converted to a single precision format exponent, and the significand is rounded according to the setting of the rounding control bits in the FP status word. The load direct double binary FPR instruction transfers data from one doubleword of memory to bits 0-63 of one of the FPRs. No format conversion is made. The store direct double binary FPR instruction transfers data from bits 0-63 of one of the FPRs to one doubleword of memory. No format conversion is made. The load direct double binary FPR and...