Browse Prior Art Database

Self-Clearing Status Register

IP.com Disclosure Number: IPCOM000040432D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Corkell, AF: AUTHOR [+3]

Abstract

This article describes a circuit arrangement which prevents losing status when clearing a latching status register. A status register in a machine can be made to be either transparent or latching. A transparent status register would always reflect the present status, and a latching status register would remember that a condition occurred after that condition went away. For error conditions a latching status register is much preferred, so that one can see what caused an error after it occurred. The problem with latching status registers is that after the status is read, it must be cleared, so that new status can be latched. This must be done in a way such that no status is lost. Status is lost when a new condition puts a value in the status register between the time it was read and the time it was cleared.

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Self-Clearing Status Register

This article describes a circuit arrangement which prevents losing status when clearing a latching status register. A status register in a machine can be made to be either transparent or latching. A transparent status register would always reflect the present status, and a latching status register would remember that a condition occurred after that condition went away. For error conditions a latching status register is much preferred, so that one can see what caused an error after it occurred. The problem with latching status registers is that after the status is read, it must be cleared, so that new status can be latched. This must be done in a way such that no status is lost. Status is lost when a new condition puts a value in the status register between the time it was read and the time it was cleared. One approach to the problem requires the programmer to explicitly reset each bit of the status register with a command. This approach can be quite cumbersome and time consuming. The approach presented herein is to reset only the bits that were actually read. The implementation is in hardware and requires no programming support. The circuit which implements the status register of this disclosure is shown in the drawing. The actual status is stored in the first flip-flop 2, achieved by running on input line 4, the signal whose status is being monitored, into the clock input of the flip-flop 2. The data input of this flip-flop is tied...