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Structured CMOS Physical Design

IP.com Disclosure Number: IPCOM000040441D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Cases, M: AUTHOR [+4]

Abstract

A technique is described whereby CMOS technology is used to create a unique cell design which is constructed from a model cell called a template. The template then becomes the basis for all circuit books used throughout the chip design. The template enhances the creation of (Image Omitted) circuits due to its "built-in" structure, since it is topologically programmable by virtue of its ability to be personalized with contacts and wires without changing the base template. The template described herein is unique in that it is designed to allow the height dimension to be varied in multiples of grid increments. The required number of grid increments is determined by the number of wiring channels needed to connect the basic template, and/or the minimum area necessary to fit the required devices to the template.

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Structured CMOS Physical Design

A technique is described whereby CMOS technology is used to create a unique cell design which is constructed from a model cell called a template. The template then becomes the basis for all circuit books used throughout the chip design. The template enhances the creation of

(Image Omitted)

circuits due to its

"built-in" structure, since it is topologically programmable by virtue of its ability to be personalized with contacts and wires without changing the base template. The template described herein is unique in that it is designed to allow the height dimension to be varied in multiples of grid increments. The required number of grid increments is determined by the number of wiring channels needed to connect the basic template, and/or the minimum area necessary to fit the required devices to the template. The width of each template is fixed and is determined by the electrical specifications of the circuit. The width of the final book is altered by adding templates in parallel and by expanding the shapes which interconnect the two or more templates in parallel. The ratio of height to width of the final book is controlled in order to allow the book to assume the shape most conducive to wiring. A typical AND circuit, as shown in the top section of Fig. 1, has three inputs in the structured design.

The complete structure has two templates of various heights, a three-input AND and a four-input AND circuit. Electrical modelling for logic blocks of this type is simplified due to the regularity of the silicon layouts. Al...