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Eight-Bit to Sixteen-Bit Memory Converter

IP.com Disclosure Number: IPCOM000040442D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR [+4]

Abstract

A technique is described whereby a computer circuit provides a means of enabling a sixteen-bit microprocessor to execute programs directly from an eight-bit-wide memory array. The concept uses a sixteen-bit to eight-bit memory converter to convert a single standard eight-bit wide memory array so that it appears to be sixteen-bits wide. This enables sixteen-bit microprocessors to utilize inexpensive eight-bit memory devices and also reduces the amount of circuitry which would normally be required for sixteen-bit arrays. The technique used also enables circuitry to be implemented utilizing left-over logic already existing on circuit cards. (Image Omitted) The basic design of the sixteen- to eight-bit memory converter is shown in Fig. 1. The converter 10 consists of control logic unit 11, latch 12 and tri-state driver 13.

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Eight-Bit to Sixteen-Bit Memory Converter

A technique is described whereby a computer circuit provides a means of enabling a sixteen-bit microprocessor to execute programs directly from an eight- bit-wide memory array. The concept uses a sixteen-bit to eight-bit memory converter to convert a single standard eight-bit wide memory array so that it appears to be sixteen-bits wide. This enables sixteen-bit microprocessors to utilize inexpensive eight-bit memory devices and also reduces the amount of circuitry which would normally be required for sixteen-bit arrays. The technique used also enables circuitry to be implemented utilizing left-over logic already existing on circuit cards.

(Image Omitted)

The basic design of the sixteen- to eight-bit memory converter is shown in Fig. 1. The converter 10 consists of control logic unit 11, latch 12 and tri-state driver 13. During a write cycle, sixteen-bit microprocessor 14 places a sixteen-bit word onto the data bus. Control logic unit 11 enables high-byte tri-state driver 15 so as to provide the control signals for writing into memory. Next, the high-byte portion of the sixteen-bit bus is tri-stated and the low-byte tri-state driver 16 is enabled.

The low address bit (A0) is then toggled to point to the next byte in the eight-bit memory 17. The control signals write the low byte into memory through tri-state driver 13. The timing diagram for the write cycle is shown in Fig. 2. During the read cycle, while the address is va...