Browse Prior Art Database

Microprocessor-Controller Communication Technique

IP.com Disclosure Number: IPCOM000040446D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Andrews, CL: AUTHOR [+2]

Abstract

Parallel bus communication between a central microprocessor and subordinate microprocessors can accommodate interrupt-driven controllers of different types and provide full checking of all transmitted data. The communication link is a star configuration with the central controlling processor, or main engine, as the nucleus, and any number of subordinate processors, also referred to as controllers, forming the arms of the star. (Image Omitted) The main engine, such as an Intel 80186, uses half-duplex communication via an eight-bit parallel bus with several printer mechanism controllers, such as carriage, ribbon, print and stacker mechanisms. The controllers may be Intel 8051 microprocessors with the communication interface I/O mapped to the main engine.

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Microprocessor-Controller Communication Technique

Parallel bus communication between a central microprocessor and subordinate microprocessors can accommodate interrupt-driven controllers of different types and provide full checking of all transmitted data. The communication link is a star configuration with the central controlling processor, or main engine, as the nucleus, and any number of subordinate processors, also referred to as controllers, forming the arms of the star.

(Image Omitted)

The main engine, such as an Intel 80186, uses half-duplex communication via an eight-bit parallel bus with several printer mechanism controllers, such as carriage, ribbon, print and stacker mechanisms. The controllers may be Intel 8051 microprocessors with the communication interface I/O mapped to the main engine. Communication is handled by two code packages, both labeled COMMPATH, and common hardware interfaces between the main engine and each controller. One code package handles communication in the engine, fielding interrupts from all the subordinate processors as required. The second package, which is common to all the controllers, oversees communication for each individual controller while running at the lowest interrupt priority. In each controller, COMMPATH code executes periodically in a simple background loop. This loop starts outbound messages whenever available. In the main engine, COMMPATH can be called directly by the controlling code to start sending any new message. Messages are in a prescribed form four to fourteen bytes long and are stored in a fourteen-byte input or fourteen-byte output buffer.

(Image Omitted)

First (header) and last (trailer) message bytes are distinctively designated, and the second byte contains the total number of message bytes being transferred, including the header, trailer, and message length bytes. Header and trailer bit patterns, such as F1-F5 or E1-E5 and 11-15 or 21-25, specify both message direction and source. The distinctive byte forms do not preclude their use in message bytes, since COMMPATH code looks for specified bit patterns only when they are expected. The header and trailer bytes maintain synchronization and prevent confusion caused by other controllers initiating simultaneous or unexpected messages. In the main engine, each controller interface may be assigned unique interrupts and unique addresses from which inputs are read. Each controller has two single-byte buffers, one input and one output, which the main engine can access. Messages are transmitted one byte at a time, and the receiving microprocessor echoes the received byte. During an outbound message from the main engine, COMMPATH sends the first byte and relinquishes control until an echo is received from the addressed controller. The interface produces an interrupt, and the COMMPATH code reads internal status bits to determine whether the byte

(Image Omitted)

is an echo or a new byte. If the byte is an echo, a comparison is ma...