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CLOCK EXPANDER WITH MUTUALLY REFERENCED CURRENT SWITCHES

IP.com Disclosure Number: IPCOM000040461D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

This article concerns reducing the circuit count (and required chip area) in existing clock pulse expander logic by eliminating cascode switch circuitry and employing instead mutually referenced current switches (MRCS) logic.

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CLOCK EXPANDER WITH MUTUALLY REFERENCED CURRENT SWITCHES

This article concerns reducing the circuit count (and required chip area) in existing clock pulse expander logic by eliminating cascode switch circuitry and employing instead mutually referenced current switches (MRCS) logic.

Fig. 1 illustrates clock pulse expander logic employing MRCS. A set dominate set/reset latch with a delay element in the feedback path is featured which generates the desired pulse width. Also, two distinct logic swings, one shifted one-half of a full swing from the other, are used for the set and reset inputs in order to perform the pulse width expansion function. The external + clock pulse shown in Fig. 1 is assumed to swing between 0.0 volts and +0.6 volt while all others swing between -0.3 volt and +0.3 volt. As shown in the figure, clock pulse expander logic consists of the following three components: Set Dominate Set/Reset Latch [1]

MRCS AND gate [2]

Delay element [3] As long as the + input clock pulse [1] is maintained at 0.6 V, the delayed reset pulse cannot reset the latch. If the + clock pulse is narrower than W, the latched polarity is held for a duration of W. Thus, the latch polarity is the desired internal clock and the AND gate [2], which allowed for possible inhibition of the expander logic, may be removed. The complex clock pulse expander logic is thus reduced to one simple current switch and one delay element. If the external clock pulse and inhibit signal do not have...