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Shared Planar Interrupt for Personal Computers

IP.com Disclosure Number: IPCOM000040479D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Huynh, DH: AUTHOR [+2]

Abstract

A technique is described whereby the number of interrupts available in personal computers (PCs) is expanded by utilizing a method of sharing interrupt controls within a planar board. This is accomplished without increasing the number of interrupt controllers. Functional interrupt compatibility with existing PCs continues to be maintained. Certain PCs, such as the IBM PC and PC XT, utilize an eight- channel interrupt controller, where interrupt 0 is assigned to the timer, interrupt 1 is assigned to the keyboard and interrupts 2 - 7 are assigned to input/output (I/O) devices. Other PCs, such as the IBM PC AT, provide a second interrupt controller in order to expand the number of interrupts in the system.

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Shared Planar Interrupt for Personal Computers

A technique is described whereby the number of interrupts available in personal computers (PCs) is expanded by utilizing a method of sharing interrupt controls within a planar board. This is accomplished without increasing the number of interrupt controllers. Functional interrupt compatibility with existing PCs continues to be maintained. Certain PCs, such as the IBM PC and PC XT, utilize an eight- channel interrupt controller, where interrupt 0 is assigned to the timer, interrupt 1 is assigned to the keyboard and interrupts 2 - 7 are assigned to input/output (I/O) devices. Other PCs, such as the IBM PC AT, provide a second interrupt controller in order to expand the number of interrupts in the system. The concept described herein provides a method of expanding the number of interrupts utilizing only one interrupt controller, while continuing to maintain functional compatibility with existing PCs. The interrupt controller function is incorporated within the I/O support gate array circuitry in the planar board of the PC. Eight levels of interrupt are provided with level 0 as the highest priority and level 7 as the lowest priority. All eight levels are used in a manner compatible with existing PCs which incorporate only one interrupt controller, except level 1. In this case, level 1 is shared by the keyboard port, mouse port, and realtime clock circuitry. The concept provides three new features to the interrupt controller logic so as to allow the sharing of interrupt level 1. The three features are: a)

Interrupt level 1 will always be level sensitive. b) The interrupt vector returned by the interrupt

controller when acknowledging interrupt 1 will

always be at vector 71H.

c) Interrupt controller extension registers A0H and

A1H...