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Prime Interleave Addressing Mechanism

IP.com Disclosure Number: IPCOM000040500D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Brady, JT: AUTHOR

Abstract

A memory system having a prime number of interleaving units is described wherein memory addresses can be determined by only adding real addresses shifted to proper offsets. Address selection calculations for a memory with interleave P are: word_in_memory_unit address = INT(real_address/P) memory_unit address = INT(FRACT(real_address/P)*P (Image Omitted) If P = 2(2n+1) - 1, n / 1, then the reciprocal of P would become a repeating fraction which has 2n zeros followed by a one. This allows the product (1/P) * real_address to be formed by adding a plurality of real addresses each shifted to a proper offset. The result of the addition is a sufficiently close approximation of real_address/P.

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Prime Interleave Addressing Mechanism

A memory system having a prime number of interleaving units is described wherein memory addresses can be determined by only adding real addresses shifted to proper offsets. Address selection calculations for a memory with interleave P are: word_in_memory_unit address = INT(real_address/P)

memory_unit address = INT(FRACT(real_address/P)*P

(Image Omitted)

If P = 2(2n+1) - 1, n / 1, then the reciprocal of P would become a repeating fraction which has 2n zeros followed by a one. This allows the product (1/P) * real_address to be formed by adding a plurality of real addresses each shifted to a proper offset. The result of the addition is a sufficiently close approximation of real_address/P. The integer (INT) portion of the result is the word_in_memory address, and the fraction (FRACT) portion is used in the calculation of the memory_unit address: memory_unit address = INT(FRACT*P) = INT((FRACT*(P-1))-FRACT) Fig. 1 illustrates the calculations of the word_in_memory address and memory_unit address in a 256 Mbyte memory system with 127 way interleave (P=127) and double word (8 byte) per interleave. Fig. 2 illustrates the calculations for the same system when there is 511 way interleave (P=511).

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