Browse Prior Art Database

Low Power Word Line Driver

IP.com Disclosure Number: IPCOM000040529D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Klein, W: AUTHOR [+3]

Abstract

Proposed is a circuit improvement in a word line driver for gated arrays with Harper-type cells which drastically reduce the power consumption, without impairing the performance. Some types of fast bipolar memory cells, such as Harper-type and CTS (Complementary Transistor Switch) cells, comprise two word lines. The driver and decoder circuits for those cells are very complex and marked by high power dissipation to reach the required performance. The figure shows an improved word line driver with a decoder. Word line decoder TD1 ... TD4 is controlled by input signals A1 and A2 and is activated by clock signal CL (down level). Node OP is pulled up, turning transistor T11 on. Then the charge stored in the saturated PNP transistor T14 (PNP current mirror) and on charge supply line CSL is discharged by transistor T13.

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Low Power Word Line Driver

Proposed is a circuit improvement in a word line driver for gated arrays with Harper-type cells which drastically reduce the power consumption, without impairing the performance. Some types of fast bipolar memory cells, such as Harper-type and CTS (Complementary Transistor Switch) cells, comprise two word lines. The driver and decoder circuits for those cells are very complex and marked by high power dissipation to reach the required performance. The figure shows an improved word line driver with a decoder. Word line decoder TD1 ... TD4 is controlled by input signals A1 and A2 and is activated by clock signal CL (down level). Node OP is pulled up, turning transistor T11 on. Then the charge stored in the saturated PNP transistor T14 (PNP current mirror) and on charge supply line CSL is discharged by transistor T13. This current spike produces an additional current spike in T12 (NPN current mirror), turning on PNP transistor T10 very rapidly. As soon as T3 has been turned on, the upper word line UWL is charged. Parallel thereto, T1 is turned off by TD4 after clock signal CL has been activated (down level). Consequently, T2 is also turned off, and the lower word line LWL is charged by the cell currents.

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