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Improved Vector Operations in Store-In Cache Machines

IP.com Disclosure Number: IPCOM000040539D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+6]

Abstract

This invention provides improved cache performance in machines with store-in caches that use large vector operands. This performance advantage is obtained by performing specific vector storage operations directly to memory, that is, by storing "around" rather than "in" the cache. The cache represents a performance sensitive area for processors with a vector processing capability. When such processors derive their operand activity from a store-in cache, an improvement can be realized for a subset of Vector Register Store (VRS) operations. When the VRS operations represent an update to the entire line in memory, several efficiencies can be realized.

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Improved Vector Operations in Store-In Cache Machines

This invention provides improved cache performance in machines with store-in caches that use large vector operands. This performance advantage is obtained by performing specific vector storage operations directly to memory, that is, by storing "around" rather than "in" the cache. The cache represents a performance sensitive area for processors with a vector processing capability.

When such processors derive their operand activity from a store-in cache, an improvement can be realized for a subset of Vector Register Store (VRS) operations. When the VRS operations represent an update to the entire line in memory, several efficiencies can be realized.

The processor, by detecting that a series of stores generated by a VRS operation will completely update one or more lines of the main memory, can: 1)suppress the line fetch from memory to bring this line into the cache 2)initiate a castout action from the cache where the castout data is passed directly from the vector registers to the SCE and bypasses

the cache, and 3)either update or invalidate the line in the cache which is the area into which the store activity would be generated. Allowing the VRS to perform a "store-wherever" function in this special case
(i.e., on complete line stores) can be extended without additional hardware to partial line stores. It is required that in such a circumstance, the line must reside in the cache and be fetched into the cache if...