Browse Prior Art Database

FIFO Register for Graphics Display

IP.com Disclosure Number: IPCOM000040552D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Taylor, JL: AUTHOR

Abstract

This disclosure is a modification of the arrangement shown in the IBM Technical Disclosure Bulletin 29, 3164-3165 (December 1986), to make the FIFO (first-in, first-out) more general purpose and to provide a fast LSSD bit-sliced FIFO of arbitrary width and depth which will accept and supply data at irregular intervals. The disclosure relates to any system where data must be queued between processes, e.g., a display where page mode bursts of data are queued for serialization or where data to be written to memory must be queued so that bursts of write cycles may be interleaved with refresh reads. The basic bit-slice for the design is shown in Fig. 1. The bit- slice contributes two layers to the depth of the FIFO and comprises control logic and FIFO data-holding registers.

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FIFO Register for Graphics Display

This disclosure is a modification of the arrangement shown in the IBM Technical Disclosure Bulletin 29, 3164-3165 (December 1986), to make the FIFO (first-in, first-out) more general purpose and to provide a fast LSSD bit-sliced FIFO of arbitrary width and depth which will accept and supply data at irregular intervals. The disclosure relates to any system where data must be queued between processes, e.g., a display where page mode bursts of data are queued for serialization or where data to be written to memory must be queued so that bursts of write cycles may be interleaved with refresh reads. The basic bit-slice for the design is shown in Fig. 1. The bit- slice contributes two layers to the depth of the FIFO and comprises control logic and FIFO data-holding registers. Two single-bit registers (R1 and R2) flag whether valid data is held in the L1 or L2 layer of the data-holding registers. Data available and data required signals are generated for connection to neighboring bit-slices, and corresponding inputs are shown. The circuit is operated with multiple clocks under LSSD rules. All inputs are sampled at C-clock time and appropriate A, B and C clocks are generated. The A and B clocks are used to shift data down the FIFO. The C and B clocks are used to load data into the FIFO.

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Data may be supplied to and/or removed from the FIFO on any C clock, including consecutive C clocks. Data supplied to the FIFO on one C clock becomes available at the output of the FIFO in time for the next C clock u...