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# Selective Negator

IP.com Disclosure Number: IPCOM000040556D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 57K

IBM

## Related People

Bowater, RJ: AUTHOR [+2]

## Abstract

One way of forming the negative of a "twos complement" number is by inverting all bits of the number more significant than the least significant bit of value '1'. The bits are selected for inversion by means of an inversion mask which has the property of having '1's at all bit positions more significant than the least significant '1' and '0's elsewhere. When the inversion mask is combined with the number using the Boolean Exclusive- OR function, the '1's in the inversion mask cause the related bits of the number to be inverted. The '0's in the inversion mask cause the related bits of the number to remain unchanged. The logic diagram for the Selective Negator appears in Fig. 1. The diagram shows a basic n-bit implementation. Both the input W and the output N are "twos complement" numbers, which can be positive or negative.

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Selective Negator

One way of forming the negative of a "twos complement" number is by inverting all bits of the number more significant than the least significant bit of value '1'. The bits are selected for inversion by means of an inversion mask which has the property of having '1's at all bit positions more significant than the least significant '1' and '0's elsewhere. When the inversion mask is combined with the number using the Boolean Exclusive- OR function, the '1's in the inversion mask cause the related bits of the number to be inverted. The '0's in the inversion mask cause the related bits of the number to remain unchanged. The logic diagram for the Selective Negator appears in Fig. 1. The diagram shows a basic n-bit implementation. Both the input W and the output N are "twos complement" numbers, which can be positive or negative. If it is required to extend the output number beyond n bits, with an input of n bits, then the most significant bit (sign bit), N(n), can be used for all more significant bits.

(Image Omitted)

The inversion mask is generated by cumulatively ORing the bits of the n-bit input number W. The least significant bit of the input, W(1), is never inverted and is passed directly to the least significant bit, N(1), of the output number N. The chain of two-input OR gates is the simplest form of inversion mask generation. The equations for the inversion mask I are as follows:

I(1) = 0

I(2) = W(1)

I(3) = W(1)+W(2)

I(4) = I(3)+W(3)

: :

: :

I(n-1) = I(n-2)+W(n-2)

I(n) = I(n-1)+W(n-1) The delay to the most significant bit of the inversion mask is the cumulative delay of n-2 OR gates. In applications where the data input to output path is speed critical, the inversion mask can be generated using wider OR gates, look-ahead or parallel processing techniques to increase the speed. The inversion mask is ANDed with the selection control signal, NEGATE. If NEGATE=1, then the generated inversion mask is passed to the XOR gates for combination with the input number. '1's in the inversion mask cause the related bits of the input number to be inverted. The output is therefore the negative of the input (negative selected). If NEGATE=0, then the inversion mask is gated to all '0's, which prevents any of the bits of the input number being inverted. Hence the output is equal to the input (positive selected). The delay from the s...