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Browse Prior Art Database

High Performance Multi-Chip Module

IP.com Disclosure Number: IPCOM000040557D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Olson, LT: AUTHOR

Abstract

A multi-chip ceramic module design enhances the wirability and electrical performance capability of metallized ceramic polyimide (MCP) chip carriers. The module is constructed and works as described below. A single-chip MCP module has two levels of metal, a bottom layer M1 and a top layer M2 (Fig. 1A). The module has pins which are flush, or flush with a chamfer, on the top surface module. The M1 metal is used for power plane(s), and the M2 level contains all signal conductors. Fig. 1B depicts a ceramic substrate containing two levels of metal M3 and M4. Signal lines are placed on M3, and power plane(s) on M4. A square hole, which is slightly larger than the chip (Fig. 1A), is located at the center of the substrate. A matrix of pads which access M3 or M4 planes by vias are also shown on the top surface.

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High Performance Multi-Chip Module

A multi-chip ceramic module design enhances the wirability and electrical performance capability of metallized ceramic polyimide (MCP) chip carriers. The module is constructed and works as described below. A single-chip MCP module has two levels of metal, a bottom layer M1 and a top layer M2 (Fig. 1A). The module has pins which are flush, or flush with a chamfer, on the top surface module.

The M1 metal is used for power plane(s), and the M2 level contains all signal conductors. Fig. 1B depicts a ceramic substrate containing two levels of metal M3 and M4. Signal lines are placed on M3, and power plane(s) on M4. A square hole, which is slightly larger than the chip (Fig. 1A), is located at the center of the substrate. A matrix of pads which access M3 or M4 planes by vias are also shown on the top surface.

(Image Omitted)

Fig. 2 shows the assembled module after the substrate (Fig. 1B) is placed over and connected to the single-chip module (Fig. 1A). Although this connection can be implemented in several ways, i.e., pads to pin heads, pads to pad via solder ball as in controlled collapse chip connector (C-4), the C-4 chamfered flush pin surface method is preferable. The resultant package is actually a 4S structure. The outer two planes M1 and M4 form a triplate structure which sandwiches the M2 and M3 signal layers. The C-4 connections provide access between all levels as well as a separation between M2 and M3. This tightly stacked module will not impact t...