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# 15 Digit SHIFT Unit

IP.com Disclosure Number: IPCOM000040558D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 4 page(s) / 64K

IBM

## Related People

Guignard, S: AUTHOR [+2]

## Abstract

This Shift Unit is an hexadecimal digit (4n-bit) shifter operating on 64 bits and performing 0 to 15 digit shifts left or right. 1.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 76% of the total text.

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15 Digit SHIFT Unit

This Shift Unit is an hexadecimal digit (4n-bit) shifter operating on 64 bits and performing 0 to 15 digit shifts left or right. 1. Principle The subject shift Unit is a very fast unit: its logic is implemented through only two simple logic stages detailed hereafter: The first stage performs: 1) 0 shift (pass thru) with the associated control: NS1

2) 8 digit left shift " " " " 8L

3) 8 digit right shift " " " " 8R

4) 16 digit right shift " " " " 16R The second stage performs: 1) 0 shift (pass thru) with the associated control: NS2

2) 1 digit left shift " " " " 1L

3) 2 digit left shift " " " " 2L

4) 3 digit left shift " " " " 3L

5) 4 digit left shift " " " " 4L

6) 5 digit left shift " " " " 5L

7) 6 digit left shift " " " " 6L

8) 7 digit left shift " " " " 7L The desired shift is obtained by setting the correct combination of the first stage control lines: NS1, 8L, 8R, 16L and the second stages ones: NS2, 1L, 2L, 3L, 4L, 5L, 6L, 7L. Desired Shift 1st stage CTL lines 2nd stage CTL lines 15 digit LEFT 8L 7L

14 digit LEFT 8L 6L

13 digit LEFT 8L 5L

12 digit LEFT 8L 4L

11 digit LEFT 8L 3L

10 digit LEFT 8L 2L

9 digit LEFT 8L 1L

8 digit LEFT 8L NS2

7 digit LEFT NS1 7L

6 digit LEFT NS1 6L

5 digit LEFT NS1 5L

4 digit LEFT NS1 4L

3 digit LEFT NS1 3L

2 digit LEFT NS1 2L

1 digit LEFT NS1 1L

NO SHIFT NS1 NS2

1 digit RIGHT 8R 7L

2 digit RIGHT 8R 6L

3 digit RIGHT 8R 5L

4 digit RIGHT 8R 4L

5 digit RIGHT 8R 3L

6 digit RIGHT 8R 2L

7 digit RIGHT 8R 1L

8 digit RIGHT 8R NS2

9 digit RIGHT 16R 7L

10 digit RIGHT 16R 6L 11 digit RIGHT 16R 5L

1

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12 digit RIGHT 16R 4L

13 digit RIGHT 16R 3L

14 digit RIGHT 16R 2L

15 digit RIGHT 16R 1L

16 digit RIGHT 16R NS2 Note: 16 Right may be replaced by feeding '0' on all bits. 2. Logic Implementation First stage The first stage has 4 control lines: NS1, 8L, 8R, 16R. These lines control a stage of 92 AND/OR 2x2 gates (Fig.
1) used as multiplexers. Each AND/OR 2x2 receives either:

- The direct non-shifted bit from the data bus

controlled with NS1.

- The 32nd bit directly to its left corresponding to

the 8th left digit controlled with 8L. or

- The direct non-shifted bit from the data bus

controlled with NS1.

- The 32nd bit directly to its right corresponding to

the 8th right digit controlled with 8R. nor

- The 32nd bit directly to the right corresponding to

the 8th right digit controlled with 8R.

- The 64th bit directly to the right corresponding to

the 16 right digit controlled with 16R. The 2x2 input AND/OR are feeded with the 64 input data bus and the control lines (Fig. 2). The intermediate data bus between the first stage and the second stage has to be enlarged to not lose the extreme right bits when shifting the extreme right condition at the first stage, then the extreme left condition at the second stage. For that, this intermediate data bus must have 0 to 91 bit positions (extreme combinations: 8R-7L and 16R-7L). Second stage The second stage uses 2x8 AND/OR logic function (Fig. 3). The...