Browse Prior Art Database

Physical Implementation of a Modular Decoder

IP.com Disclosure Number: IPCOM000040559D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Coppens, P: AUTHOR [+3]

Abstract

This article relates to a modular decoder to be used with expandable random-access memory (RAM) macros personalized on gate arrays. The subject methodology allows a user to automatically place and wire a specified size RAM macro by simply inputting a minimum set of parameters as word and bit numbers and input/output I/O requirements. The placement and wiring are done using elementary kernels as four one-bit word four-word decoders, one-bit data in/data out block and a control block. To reduce the number of kernels required to handle and suppress via matrices needed to interconnect the word decoder inputs to address lines running in the wiring bays, the decoder architecture performs all interconnections to address lines internally to the decoder kernel.

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Physical Implementation of a Modular Decoder

This article relates to a modular decoder to be used with expandable random- access memory (RAM) macros personalized on gate arrays. The subject methodology allows a user to automatically place and wire a specified size RAM macro by simply inputting a minimum set of parameters as word and bit numbers and input/output I/O requirements. The placement and wiring are done using elementary kernels as four one-bit word four-word decoders, one-bit data in/data out block and a control block. To reduce the number of kernels required to handle and suppress via matrices needed to interconnect the word decoder inputs to address lines running in the wiring bays, the decoder architecture performs all interconnections to address lines internally to the decoder kernel. Therefore, all decoders are identical with a modulo of four-word lines, as shown in Fig. 1, and the address truth table implementation is done through an address line periodical permutation within the decoder (as shown in Fig. 2). Addresses 0 and 1 are identically connected in each decoder. Addresses 2 to 4 are shifted by one row at the inputs of each decoder, thus allowing all binary combinations to take place. In the figures, T0 to T4 and C0 to C4 identify true and complement values of the address bits 0 to 4, respectively.

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