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Method to Debug and Temp Fix Around LSSD VLSI Design Errors

IP.com Disclosure Number: IPCOM000040568D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 4 page(s) / 40K

Publishing Venue

IBM

Related People

Bassemir, RT: AUTHOR [+2]

Abstract

Problem Description: As new technologies evolve, the circuit density on chips increase. With increasing circuit counts on a single chip, several problems become more prevalent. 1) With greater circuit density more functions will be designed on single chips. Debugging these functions becomes more difficult because the designer does not have the ability to "scope" the internals of the chip. 2) Fabrication time of chips increases. A design error could stop all testing until a new chip is fabricated. 3) In the past temp fixes were used to correct design errors and allow continued testing, but as more function is placed internally on chips, the ability to apply a temp fix from chip I/O pins is greatly reduced.

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Method to Debug and Temp Fix Around LSSD VLSI Design Errors

Problem Description: As new technologies evolve, the circuit density on chips increase. With increasing circuit counts on a single chip, several problems become more prevalent. 1) With greater circuit density more functions will

be designed on single chips. Debugging these

functions becomes more difficult because the

designer does not have the ability to "scope" the

internals of the chip.

2) Fabrication time of chips increases. A design

error could stop all testing until a new chip is

fabricated.

3) In the past temp fixes were used to correct design

errors and allow continued testing, but as more

function is placed internally on chips, the

ability to apply a temp fix from chip I/O pins is

greatly reduced.

(Image Omitted)

These are the reasons so much emphasis is

placed on design verification prior to hardware

fabrication. Since there has been no design

verification system yet that can find 100% of the

design errors, one should be prepared to debug and

temp fix LSSD VLSI (level sensitive scan design -

very large-scale integration) chips. Described

below is a technique to enhance a designers

ability to debug and temp fix the hardware. General Description: To enhance the designer's ability to debug and temp fix a VLSI chip, it would be useful to have the means to bring internal chip functions off chips that normally are contained entirely on the chip. Due to I/O limitations, a designer typically will not drive unnecessary signals to chip I/O. In the test environment, however, having certain signals come off chip can make debug and temp fixes possible that were not possible before. The objective was to provide a means for the designer to get chip functions to chip I/O without having to remove and EC (engineering change) the chip. This can be done by adding some minimal logic to the chip to implement a function generator. The function generator is logic that can be controlled by the designer to generate and drive different functions off chip.

This gives the designer the flexibility to choose different internal functions to be driven off chip for use in debug and/or a temp fix. Theory of Operation: Function generator 10 consists of logic that will generate a signal from a Boolean combination of its inputs. The signal out of the function generator is programmed by using scan-only registers within the function generator. The number of inputs to the function generator is defined in the initial design and could vary from one chip to another. The single signal out leaves the VLSI chip to an engineering changeable I/O pin. The internals of the function

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generator may vary. The designer has the option to customize the generator. Fig. 2 is an example of a function generator. The scan-only latches (SOL) would select from seven predefined inputs for the function generator. Other SOLs are used to control the phase of the selected inputs. These SOLs have selected the inputs an...