Browse Prior Art Database

Auto Programming Lumped Load Off-Chip-Drivers

IP.com Disclosure Number: IPCOM000040569D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 78K

Publishing Venue

IBM

Related People

Erdelyi, CK: AUTHOR [+3]

Abstract

A system is reported which allows an FET (field-effect transistor) off-chip-driver (OCD) to drive a stable signal, with the desired characteristic, into a lumped capacitive load by dynamically programming more and more OCD segments into the driver until the output conforms with a generated reference signal. To reduce the effect of process and load variations on circuit skew, each OCD is comprised of several segments. These segments are dynamically coupled together as needed by a system of components which monitor the drive signal and compare it with an on-chip generated reference signal (RS) to insure that the OCD is properly matched to the load. RS is generated by a circuit designed to be relatively insensitive to process variations due to its size.

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Auto Programming Lumped Load Off-Chip-Drivers

A system is reported which allows an FET (field-effect transistor) off-chip-driver (OCD) to drive a stable signal, with the desired characteristic, into a lumped capacitive load by dynamically programming more and more OCD segments into the driver until the output conforms with a generated reference signal. To reduce the effect of process and load variations on circuit skew, each OCD is comprised of several segments. These segments are dynamically coupled together as needed by a system of components which monitor the drive signal and compare it with an on-chip generated reference signal (RS) to insure that the OCD is properly matched to the load. RS is generated by a circuit designed to be relatively insensitive to process variations due to its size. Because chips usually have many OCDs, the drivers cannot be made with large dimensions to be insensitive to process variations because the area consumed would be prohibitive. The block diagram shown in Fig. 1 is an overview of the scheme utilized to program a segmented OCD. Input signals (data, clock and enable) initiate a segment of the OCD by way of segment control bit latches which are set by a transition clock (TC) pulse.

The RS generator is utilized to produce a model signal which has the characteristics desired for the OCD output. OCD feedback is compared in a comparator circuit with the generated reference signal. If the rise time of the OCD signal is slower than the reference signal, a slow signal (SS) pulse is emitted at the output of the comparator. SS is utilized as a set pulse for the logic decision tree which controls the segment control bit latches. For each additional segment control bit latch set, additional OCD segments are activated. The segment control bit latches are designed to latch on a pulse that is no longer than the TC pulse. By starting at a low power level and adding segments to the OCD based on sensing SS, a higher output power level is achieved. An alternate approach would be to start at a higher power level and work down to a lower level based on sensing a fast signal (FS). The FS signal is one whose rise time is faster than the reference signal. Fig. 2 shows a schematic of the block diagram.

Input NAND logic signals include a clock pulse, data and enable lines and the NAND output signal starts low and goes high. This signal drives the reference signal and transition clock generators. The TC circuit generates a pulse whenever a downward OCD feedback transition is detected. The delayed TC drive signal is designed to operate faster than an OCD but also allows the comparator circuit to resolve its out...