Browse Prior Art Database

Off-Chip Driver Circuit

IP.com Disclosure Number: IPCOM000040580D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Bansal, JP: AUTHOR

Abstract

A tristate off chip driver (OCD) circuit disclosed herein pulls its output voltage to ground potential prior to switching from an active state to a high impedance state. The figure shows a logic implementation of an OCD 10 and a pulse generator 12. A pulse having a short duration is generated when an enable/disable input is switched from a high voltage level to a low voltage level. The width of the generated pulse is determined by the number of inverters 14 which are included in a delay chain 16. The generated pulse, which is applied to node 2 of the OCD 10, is inverted by a NAND gate 18. A positive voltage transition appearing on the output of the NAND gate 18 turns on transistor T1 thereby placing ground potential on an output node 20.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Off-Chip Driver Circuit

A tristate off chip driver (OCD) circuit disclosed herein pulls its output voltage to ground potential prior to switching from an active state to a high impedance state. The figure shows a logic implementation of an OCD 10 and a pulse generator 12. A pulse having a short duration is generated when an enable/disable input is switched from a high voltage level to a low voltage level. The width of the generated pulse is determined by the number of inverters 14 which are included in a delay chain 16. The generated pulse, which is applied to node 2 of the OCD 10, is inverted by a NAND gate 18. A positive voltage transition appearing on the output of the NAND gate 18 turns on transistor T1 thereby placing ground potential on an output node 20. Thereafter, a negative voltage transition appearing on the output of NAND gate 18 turns off transistor T1. Simultaneously, a signal, which is generated by delay chain 22 and fed through node 1, a NAND gate 24 and a NOR gate 26, turns off pull-up transistor T2. This stops the current flow from VDD and allows the output node to discharge to ground potential. Whenever the enable/disable input is switched to a high voltage level, voltage signals appearing at nodes 1 and 2 switch to high level, and the OCD 10 thereafter functions in a normal manner.

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]