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CMOS Output Inverter Circuit With Low-Power Test Output Inverter

IP.com Disclosure Number: IPCOM000040584D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Takada, S: AUTHOR

Abstract

This article describes a CMOS output inverter circuit provided with a low-power test output inverter. The test output inverter is provided in parallel with the output drive inverter and used only to produce test outputs in test mode. The CMOS output drive inverter, which consists of series-connected P-type and N-type field-effect transistors (FETs) is usually comprised of very large transistors to provide a sufficient driving ability. When operated at a high frequency for testing, such an inverter can cause a large transient current through both the FETs, increasing power consumption and generating noise signals. To prevent this, a low-power CMOS test output inverter made up of small transistors is added as a test output stage. Fig.

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CMOS Output Inverter Circuit With Low-Power Test Output Inverter

This article describes a CMOS output inverter circuit provided with a low-power test output inverter. The test output inverter is provided in parallel with the output drive inverter and used only to produce test outputs in test mode. The CMOS output drive inverter, which consists of series-connected P-type and N-type field- effect transistors (FETs) is usually comprised of very large transistors to provide a sufficient driving ability. When operated at a high frequency for testing, such an inverter can cause a large transient current through both the FETs, increasing power consumption and generating noise signals. To prevent this, a low-power CMOS test output inverter made up of small transistors is added as a test output stage. Fig. 1 shows an embodiment which comprises a CMOS test output inverter 10, a CMOS output drive inverter 20 and a control circuit 30. The output of the test output inverter 10 is connected in common with the output of the output drive inverter 20. The test output inverter

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10 can be comprised of small transistors since it is used for test purposes only. In normal mode, the control input C to the control circuit 30 is low so that an AND gate A1 is not conditioned, placing the test output of the inverter 10 at a high impedance state. On the other hand, an AND gate A2 is conditioned so that the inverter 20 operates normally in response to the output of a preceding...