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DUAL DATA TRANSFER RATE INTEGRATED DISKETTE CONTROLLER WITH FREQUENCY MULTIPLIER DATA RECOVERY CIRCUIT

IP.com Disclosure Number: IPCOM000040593D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 31K

Publishing Venue

IBM

Related People

Buhler, O: AUTHOR [+3]

Abstract

A technique is described whereby a dual data transfer rate integrated diskette controller with frequency multiplier data recovery is implemented into personal computer diskette drive circuitry to increase the functions of data transfers and to be compatible with existing software programs. The dual rate transfer controller consists of a gate array module that provides the support to a primary diskette controller and to an external analog phase lock-loop for data recovery. The gate array consists of three sections: diskette registers, write logic, and read logic. Diskette Register Section: The gate array has five registers used for configuration drive selection and diagnostics. A digital input register is used to sense the status of the diskette change line and for diagnostic purposes.

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DUAL DATA TRANSFER RATE INTEGRATED DISKETTE CONTROLLER WITH FREQUENCY MULTIPLIER DATA RECOVERY CIRCUIT

A technique is described whereby a dual data transfer rate integrated diskette controller with frequency multiplier data recovery is implemented into personal computer diskette drive circuitry to increase the functions of data transfers and to be compatible with existing software programs. The dual rate transfer controller consists of a gate array module that provides the support to a primary diskette controller and to an external analog phase lock-loop for data recovery. The gate array consists of three sections: diskette registers, write logic, and read logic. Diskette Register Section:

The gate array has five registers used for configuration

drive selection and diagnostics. A digital input register

is used to sense the status of the diskette change line and

for diagnostic purposes. There are two write-only

registers, a digital output register to control the drive

motors, drive selection and feature enable functions, and a

configuration control register used to set the data transfer

rate and to select write pre-compensation.

Write Logic Section:

This section generates the main clock and the write clock

for the diskette controller. Both of these clocks vary in

frequency depending on the data rate selected. For example,

for a 250 KB/second data rate, the main clock is a four MHz

signal with a 50% duty cycle. The write clock is a 500

KB/second signal with a positive pulse width of 250 nsec.

For the 500 KB/second data rate, the main clock is an eight

MHz signal with a 50% duty cycle, and the write clock is a

one MHz signal with a positive pulse width of 250 nsec.

Changing the data rates from 250 to 500 KB/second is done

synchronously to prevent any violation of a minimum low and

high clock time of the main clock.

A write pre-compensation delay of 125 nsec. is provided for

all tracks on write data when pre-compensation is selected.

Pre-compensation is needed because when writing flux

transitions at very high densities, one bit influences an

adjacent bit so as to shift the leading edge of both bits.

The write pre-compensation circuit shifts the bits in the

opposite direction before writing. When a bit shift occurs

on the media, the bits tend to shift back to a nominal

position. The write pre-compensation algorithm is

incorporated in the controller, and it generates two signals

to decode early, late or nominal.

Read Logic Section:

This section consists of frequency multiplication circuitry

for digitally capturing data separator requirements. The

separator consists of a digital single-shot used to

synchronize and condition the READ DATA pulses from the

drive. The single-shot is generated f...