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High Speed Circuit Implementation for Normalizing a Floating Number

IP.com Disclosure Number: IPCOM000040594D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Bansal, JP: AUTHOR [+2]

Abstract

Disclosed is a circuit for normalizing a floating-point number by simultaneously encoding leading binary zeros or binary ones and shifting the number. (Image Omitted) The technique performs the simultaneous steps of encoding and shifting the floating-point number in three stages. Referring to Fig. 1, there is shown a circuit 10 for detecting the leading zeros and ones. The circuit 10 receives the bits IO through I63 of the floating number as inputs and generates a plurality of enable outputs, E1 through E7, and control outputs, AO,O through A7,2 . The enable outputs are fed to a first level encode circuit 12 to facilitate the generation of a plurality of first stage shift control signals, E'O through E'7 and their complements, as shown in Fig. 2.

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High Speed Circuit Implementation for Normalizing a Floating Number

Disclosed is a circuit for normalizing a floating-point number by simultaneously encoding leading binary zeros or binary ones and shifting the number.

(Image Omitted)

The technique performs the simultaneous steps of encoding and shifting the floating-point number in three stages. Referring to Fig. 1, there is shown a circuit 10 for detecting the leading zeros and ones. The circuit 10 receives the bits IO through I63 of the floating number as inputs and generates a plurality of enable outputs, E1 through E7, and control outputs, AO,O through A7,2 . The enable outputs are fed to a first level encode circuit 12 to facilitate the generation of a plurality of first stage shift control signals, E'O through E'7 and their complements, as shown in Fig. 2. The first state shift control signals are fed to the first section of a three-stage shift logic circuit 14 to facilitate the first state of shifting of the

(Image Omitted)

floating-point number by zero, sixteen, thirty-two or forty-eight bits, as shown in Fig. 3. The first stage of shifting occurs after the first stage of encoding. Thereafter, the first level control signals are logically combined with the control outputs to produce a plurality of encoded second level control signals. The encoded second level control signals are fed to a second section of the shift logic circuit 14 to facilitate the second stage of shifting of the floating-point number b...