Browse Prior Art Database

Full Duplex I/O Using a 3088 Channel Subsystem

IP.com Disclosure Number: IPCOM000040602D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 35K

Publishing Venue

IBM

Related People

Anzick, WJ: AUTHOR

Abstract

An I/O protocol involves the use of two separate paths, namely, a sending path and a receiving path as a single logical path for transferring data between two CPUs through an IBM 3088 channel adapter. Channel programs used with the 3088 include a PREPARE command chained to a READ or a WRITE command. The READ and WRITE commands refer to an Indirect Address List which, for each of a plurality of data segments, contains a respective start address for each data segment. In the figure, two (host) central processing units (CPUs), which are preferably IBM System/370 computers, are interconnected through a 3088 channel adaptor. Through the 3088, data from selected addresses in CPU A may be transferred to corresponding addresses in CPU B.

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Full Duplex I/O Using a 3088 Channel Subsystem

An I/O protocol involves the use of two separate paths, namely, a sending path and a receiving path as a single logical path for transferring data between two CPUs through an IBM 3088 channel adapter. Channel programs used with the 3088 include a PREPARE command chained to a READ or a WRITE command. The READ and WRITE commands refer to an Indirect Address List which, for each of a plurality of data segments, contains a respective start address for each data segment. In the figure, two (host) central processing units (CPUs), which are preferably IBM System/370 computers, are interconnected through a 3088 channel adaptor. Through the 3088, data from selected addresses in CPU A may be transferred to corresponding addresses in CPU B. Each CPU has a "send" path and a "receive" path connected to the 3088 so that transferred data can pass along the "send" path of a first CPU, through the 3088, and to the "receive" path of the second CPU. Because of the full duplex arrangement, two CPUs can transfer data to each other simultaneously.

In the past, a PREPARE READ command to a CPU resulted in the receiving CPU interrupting its software processing. After some communication between the two CPUs involved in the READ operation, the transfer would be accomplished. In the present invention, the CPU (e.g., B) would, after processing previously received data put up a PREPARE READ for receipt of a next block of data. Accordingly, the software of CPU B is not interrupted and there is no delay after a WRITE request is made by CPU A. Stated otherwise, the software of a CPU starts the READ channel program immediately and starts the WRITE channel program when there is a block of data to transmit; and when the READ is completed, the data is processed and the READ channel program is re-started. Data transfer to a first CPU (e.g., B) can start as soon as the opposite CPU (e.g., A) begins a WRITE command.

For the READ and WRITE commands, indirect addressing is used. In particular, it is noted that typically a series of WRITE commands would have the format: 1. WRITE LENGTH ADDRESS

2. WRITE LENGTH ADDRESS

3. WRITE LENGTH ADDRESS Each WRITE command would indicate the addresses involved in each WRITE operation and the length of the block of data involved in the operatio...