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Input/Output Extension for Staked or Brazed Pin Substrate

IP.com Disclosure Number: IPCOM000040612D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Ecker, ME: AUTHOR [+2]

Abstract

A printed circuit card, or the like, is configured with insulated wire loops at specified locations to increase the input/output (I/O) capacity to a substrate without the need to drill additional holes in the card. The method is implemented in the following manner. (Image Omitted) The wire loops 1 (Fig. 1) are formed on the card 2 in the desired positions and immersed in a chemical bath 3 which strips an insulating layer 4 from the immersed end of the wire loops 1 to expose the copper 5 inside wire loop 1. The exposed copper wire 5 is then processed to provide an appropriate protective plating 6 (Fig. 2), such as Ni and a Pb/Sn alloy, for subsequent reflow bonding. As seen in Fig. 2, the card 2 with its wire loops 1 are registered for joining to a substrate 7.

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Input/Output Extension for Staked or Brazed Pin Substrate

A printed circuit card, or the like, is configured with insulated wire loops at specified locations to increase the input/output (I/O) capacity to a substrate without the need to drill additional holes in the card. The method is implemented in the following manner.

(Image Omitted)

The wire loops 1 (Fig. 1) are formed on the card 2 in the desired positions and immersed in a chemical bath 3 which strips an insulating layer 4 from the immersed end of the wire loops 1 to expose the copper 5 inside wire loop 1. The exposed copper wire 5 is then processed to provide an appropriate protective plating 6 (Fig. 2), such as Ni and a Pb/Sn alloy, for subsequent reflow bonding. As seen in Fig. 2, the card 2 with its wire loops 1 are registered for joining to a substrate 7. The segment of the substrate shown has the normal complement of staked pins 8 on a standard grid. Centrally located between any four pins in the pin grid is a staked cupped pin 9. This cupped pin 9 is positioned to correspond to the grid of wire loop members, which is part of the card 2. The module is placed so as to permit the cup 10 of the cupped pins 9 to engage the top of tinned wire loop 1. Weights are then applied to the top of the modules to assist in the placement of the pin cups 10 to the wire loop 1. The card 2 and the modules are reflowed by a vapor phase process. A hot gas plenum can be located to each side of the wave solder track so tha...