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Systematic Formulation of Design Rules for Integrated Circuit Layouts

IP.com Disclosure Number: IPCOM000040614D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Lee, J: AUTHOR

Abstract

A technique is described whereby layout design rules of integrated circuit layouts can be represented in a uniform and systematic way. The new formulation of the rules enables automatical computer programs, such as a layout compactor or a design rule checker, to perform the required design rule checking (DRC). The concept is an improvement over previously used matrix form techniques. Integrated circuit (IC) layout rules, as supplied in technology manuals, are generally described by common language descriptions and drawings to show the circumstances of various applications. When utilizing the IC layout rules in the analysis of VLSI circuit layouts, the DRC part of the operation requires that the layout rules be presented in a systematic fashion.

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Systematic Formulation of Design Rules for Integrated Circuit Layouts

A technique is described whereby layout design rules of integrated circuit layouts can be represented in a uniform and systematic way. The new formulation of the rules enables automatical computer programs, such as a layout compactor or a design rule checker, to perform the required design rule checking (DRC). The concept is an improvement over previously used matrix form techniques. Integrated circuit (IC) layout rules, as supplied in technology manuals, are generally described by common language descriptions and drawings to show the circumstances of various applications. When utilizing the IC layout rules in the analysis of VLSI circuit layouts, the DRC part of the operation requires that the layout rules be presented in a systematic fashion. One common way to represent the rules is to use the matrix form, with one minimum type space rule between each pair of masks. However, this has limitations in that the matrix of the rules is sparse, since there are no rules between many mask pairs. Also, the matrix form cannot handle a variety of rules, such as size, extension, equality and conditional rules. The concept described herein provides a framework of rules that address the deficiencies experienced in the matrix form approach and allows layout compactor programs to implement the rules efficiently. An example of the variety of IC layout rules for MOS circuitry, taking into consideration diffusion (DIF), polysilicon (PO), metal (MET) and contact (CO), is as follows: The rules typically apply between the edges of mask shapes in an IC layout. Each edge is characterized by the mask it is on and the side, inside or outside, that the spacing rule is checked. For example, edge = mask if on the inside of the shape; edge = mask otherwise. A simple rule between a pair of masks will then be represented as edge1 - edge2 = value, where value is the rule value. Examples of simple rules are as shown in Fig. 1. So as to be able to handle both m...