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High Speed and High Density Full Adder

IP.com Disclosure Number: IPCOM000040619D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Bredin, F: AUTHOR [+4]

Abstract

This article describes a Full Adder (F/A) featuring fast computation with few devices. Better performance is obtained by parallel processing of carry (CY) and sum (S). S is calculated using two serial XOR functions. These XOR pass-gates use only 6 devices and present one layer of logic delay. CY is built using a ripple carry generator. In standard F/A's, S is usually computed from CY function, and thus, this increases the sum path delay. Sum computation is carried out with 12 devices (T1...T12). Carry computation is also carried out with 12 devices (T13...T24). The total is 24 instead of 28 in commonly used F/A's. The major advantage of this circuit is that sum and carry paths are completely independent which greatly improves performance (30% faster than conventional F/A's) while using a limited number of devices.

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High Speed and High Density Full Adder

This article describes a Full Adder (F/A) featuring fast computation with few devices. Better performance is obtained by parallel processing of carry (CY) and sum (S). S is calculated using two serial XOR functions. These XOR pass-gates use only 6 devices and present one layer of logic delay. CY is built using a ripple carry generator. In standard F/A's, S is usually computed from CY function, and thus, this increases the sum path delay. Sum computation is carried out with 12 devices (T1...T12). Carry computation is also carried out with 12 devices (T13...T24). The total is 24 instead of 28 in commonly used F/A's. The major advantage of this circuit is that sum and carry paths are completely independent which greatly improves performance (30% faster than conventional F/A's) while using a limited number of devices.

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