Browse Prior Art Database

Cross Connected Busses in a Dual Microprocessor Environment

IP.com Disclosure Number: IPCOM000040622D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Ellis, CW: AUTHOR [+3]

Abstract

Shown in Fig. 1 are dual microprocessors controlling various power components of a mainframe computer. Each microprocessor has an 8-bit parallel bus connecting it to the host support computer. Each microprocessor communicates with the host only those details concerning the specific components over which it has control. Should either bus path or host port experience failure, no communication is possible between the host and the microprocessor on the failing bus. This limitation is overcome in a configuration which provides cross-connecting feed busses. The dual processor controlled input/output device allows parallel paths to each microprocessor for redundant operation as described in the following. Fig.

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Cross Connected Busses in a Dual Microprocessor Environment

Shown in Fig. 1 are dual microprocessors controlling various power components of a mainframe computer. Each microprocessor has an 8-bit parallel bus connecting it to the host support computer. Each microprocessor communicates with the host only those details concerning the specific components over which it has control. Should either bus path or host port experience failure, no communication is possible between the host and the microprocessor on the failing bus. This limitation is overcome in a configuration which provides cross-connecting feed busses. The dual processor controlled input/output device allows parallel paths to each microprocessor for redundant operation as described in the following. Fig. 2 illustrates a method of cross coupling the host data busses in such a manner that either host port can communicate with either processor.

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In operation, the device which first encounters a communication fault initiates a diagnostic request via the opposite port, in the case of the host port failure, or via interrupt to the opposite processor in the case of a microprocessor port failure. The net effect is to force a software reconfiguration such that the faulty bus is isolated and bypassed until repairs can be performed. A penalty is extracted in overall speed and increased amount of microcode required for both the host and interface processors, but will allow a system with a bus fault to...