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MICROPROCESSOR ERROR DETECTION USING a 'CHECKING on STORE' ALGORITHM

IP.com Disclosure Number: IPCOM000040625D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Bechdel, JF: AUTHOR [+2]

Abstract

A method of providing error detection and fault isolation on a general- purpose interface floating point microprocessor which has only minimal on-chip error detection is accomplished through a dual-chip scheme in which one chip checks the other. A modification to the dual-chip scheme has two single-chip floating point processors incorporated into a central electronics complex through the use of an interface adapter chip. The floating point unit (FPU) works as described in the following. The FPU is a three-chip set consisting of an interface adapter and two custom-designed single-chip floating point processor chips. The unit operates as a bus unit on the processor bus and receives all instructions from the instruction processing unit (IPU).

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MICROPROCESSOR ERROR DETECTION USING a 'CHECKING on STORE' ALGORITHM

A method of providing error detection and fault isolation on a general- purpose interface floating point microprocessor which has only minimal on-chip error detection is accomplished through a dual-chip scheme in which one chip checks the other. A modification to the dual-chip scheme has two single-chip floating point processors incorporated into a central electronics complex through the use of an interface adapter chip. The floating point unit (FPU) works as described in the following. The FPU is a three-chip set consisting of an interface adapter and two custom-designed single-chip floating point processor chips. The unit operates as a bus unit on the processor bus and receives all instructions from the instruction processing unit (IPU). The FPU is a self-contained processor and, once fed an instruction, may run independently from the IPU. Limited instruction pipelining is obtained

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by allowing the interface adapter to accept and hold the next floating point instruction while the dual-chip floating point processor is executing the current instruction. The floating point assist processor (FPAP) is a single-chip processor which employs a general-purpose interface to allow its attachment as a slave processor (receiving commands and data from a host but executing this information independently) to other computer systems. All computations are implemented as register-to-register instructions. The chip utilizes two separate arithmetic logic units (exponent and fraction) to implement floating point arithmetic. The interface adapter performs a protocol conversion function, translating a parallel processor bus interface protocol into the general-purpose serial interface protocol required. In addition, this chip provides comparator hardware for the result-checking operations. In order to meet design requirements, the FPU implements a dual FPAP configuration. This allows result checking between the two chips. Controls were added to allow the chip to be preset as either a "master" or a "slave". As a master, it drives...