Browse Prior Art Database

BOOTH ENCODER/SELECTOR COMPARATOR for HIGH SPEED MULTIPLIER

IP.com Disclosure Number: IPCOM000040626D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 30K

Publishing Venue

IBM

Related People

Bredin, F: AUTHOR [+4]

Abstract

Today processing requires very high speed multiplication. Arithmetic multiplication is usually realized as conditions of partial product. One of the design constraints is, then, to reduce the number of additions in order to speed up the operation. (Image Omitted) Some techniques, such as the Booth's method, have been previously proposed. The present disclosure shows how this method can be efficiently respected, implemented in CMOS technology in terms of speed and density. The first part of this operation requires encoding 3 bits of the multiplier to generate Booth coefficients. These will be then used by a selector/comparator circuit, as shown in Fig. 1. The Booth coefficients generated are -2, -1, 0, 1, 2.

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BOOTH ENCODER/SELECTOR COMPARATOR for HIGH SPEED MULTIPLIER

Today processing requires very high speed multiplication.

Arithmetic multiplication is usually realized as conditions of partial product. One of the design constraints is, then, to reduce the number of additions in order to speed up the operation.

(Image Omitted)

Some techniques, such as the Booth's method, have been previously proposed. The present disclosure shows how this method can be efficiently respected, implemented in CMOS technology in terms of speed and density. The first part of this operation requires encoding 3 bits of the multiplier to generate Booth coefficients. These will be then used by a selector/comparator circuit, as shown in Fig. 1. The Booth coefficients generated are -2, -1, 0, 1, 2. The truth table of the Booth encoder function is shown below: INPUTS OUTPUTS

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Yj+1 Yj Yj-1 CP 1X 2X

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 1 0

0 1 1 0 0 1

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 1 1 0

1 1 1 1 0 0 where:Yj-1,

Yj, Yj+1 3 bits of the multiplier CP is the sign bit 1X is the "1" term (LSB) 2X is the "2" term (MSB) The outputs are active at "1" level. The selector/comparator (SEL/COMP) encodes the multiplicand by using the Booth coefficients. The truth table is given below: INPUTS OUTPUTS

______________________________________________________________
where Xi, Xi+1 2 bits of the multiplicand Xi-- complement of Xi BOOTH ENCODER/SELECTOR COMPARATOR FOR HIGH SPEED MULTIPLIER - Continued One can improve performance and densi...