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System Bus Adapter for Attaching a General Usage Floating Point Processor

IP.com Disclosure Number: IPCOM000040630D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Bechdel, JA: AUTHOR [+3]

Abstract

In a system having a microcoded instruction processing unit (IPU) there are several choices for implementing floating point capability. One possibility is to integrate an existing or general usage floating point processor. To do this, the system must either be designed to accommodate the interface of the floating point processor or a separate interfacing mechanism must be provided. A described floating point unit (FPU) system bus adapter provides a means to employ a single bus, general usage floating point processor in an intermediate-sized system having separate busses for commands, operands, and data in addition to a specific control protocol. The adapter works as described in the following. As seen in Fig.

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System Bus Adapter for Attaching a General Usage Floating Point Processor

In a system having a microcoded instruction processing unit (IPU) there are several choices for implementing floating point capability. One possibility is to integrate an existing or general usage floating point processor. To do this, the system must either be designed to accommodate the interface of the floating point processor or a separate interfacing mechanism must be provided. A described floating point unit (FPU) system bus adapter provides a means to employ a single bus, general usage floating point processor in an intermediate- sized system having separate busses for commands, operands, and data in addition to a specific control protocol. The adapter works as described in the following. As seen in Fig. 1, two single bus general usage floating point processors are attached to an intermediate-sized system via a system bus adapter. Two identical floating point processors, master and slave, are used for comparison to improve error detection capability. The adapter and the two floating point processors are referred to, collectively, as the FPU. The F-bus between the adapter and the floating point processors is a bidirectional path over which commands, operands and data are passed. The C-bus transmits commands from the

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IPU to the FPU, the A-bus is used to send information regarding which floating point registers, if any, are to participate in the instruction, and the D-bus is used to send the actual data to and from the FPU. Fig. 2 is a conceptual depicti...