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Multiple Use of Dram Control Inputs to Reduce Testing Time

IP.com Disclosure Number: IPCOM000040631D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Clinton, MP: AUTHOR [+6]

Abstract

A memory array which is divided into two halves, AX 10 and AY 20, is shown in the figure. The Data Input/Output for Bit N (DI/O-N) 30 is used to write into AX through X-IN 12 and AX-N 14 or into AY through Y IN 22A and AY-N 24. The array AX is read out through X-OUT 16A to N-OUT 18, an Off Chip Driver (OCD), which drives out through pad DI/O-N 30. Array AY is written into through Y-IN 22A and AY-N 24 and read out through Y-OUT 16B to N-OUT 18 in a similar fashion. A control pin DS/DG-N 40 is used to block storage of Bit N during a normal write cycle to AX or AY through X-IN 12 or Y-IN 22A or to block the read out of Bit N through X-OUT 16A or Y-OUT 16B during a normal read cycle if desired. DS/DG-N thus allows partial storing or output masking of the individual array bits.

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Multiple Use of Dram Control Inputs to Reduce Testing Time

A memory array which is divided into two halves, AX 10 and AY 20, is shown in the figure. The Data Input/Output for Bit N (DI/O-N) 30 is used to write into AX through X-IN 12 and AX-N 14 or into AY through Y IN 22A and AY-N 24. The array AX is read out through X-OUT 16A to N-OUT 18, an Off Chip Driver (OCD), which drives out through pad DI/O-N 30. Array AY is written into through Y-IN 22A and AY-N 24 and read out through Y-OUT 16B to N-OUT 18 in a similar fashion. A control pin DS/DG-N 40 is used to block storage of Bit N during a normal write cycle to AX or AY through X-IN 12 or Y-IN 22A or to block the read out of Bit N through X-OUT 16A or Y-OUT 16B during a normal read cycle if desired. DS/DG-N thus allows partial storing or output masking of the individual array bits. The addition of blocks Y-IN 22B and N + X OUT 26 allows the control pin DS/DG-N to be used as an Input/Output pin for AY at the same time as DI/O- N is being used as an Input/Output pin for AX. Thus, during manufacturing testing of the memory array, AX and AY are tested simultaneously, reducing the test time in half. A write signal (W) and a read signal (R) control the inputs and outputs during normal operation, along with the X Select (SX) and Y Select (SY) controls. A Test SIGNAL (T) enables AX and AY to be used at the same time and could be applied by the tester or in some cases generated internally by two external control signals wh...