Browse Prior Art Database

Force Only Device Testing

IP.com Disclosure Number: IPCOM000040645D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Bula, O: AUTHOR [+3]

Abstract

A technique is reported for testing CMOS semiconductor devices at true device rates in a impedance-controlled environment favorable to the test system and which eliminates on-chip switching transients. Off-chip-driver (OCD) switching during chip testing may simultaneously cause switching transients on chip, a problem associated with large pinout VLSI N/CMOS and bipolar devices during chip testing. By inhibiting OCD switching during functional testing, transient switching problems are eliminated. Through the utilization of a comparator circuit on all OCDs, as shown in the figure, only forced data from a tester is used to functionally test a chip. Each OCD is disabled through a control pin 10 which places OCD 11 into a high impedance state (tri-state) during a test.

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Force Only Device Testing

A technique is reported for testing CMOS semiconductor devices at true device rates in a impedance-controlled environment favorable to the test system and which eliminates on-chip switching transients. Off-chip-driver (OCD) switching during chip testing may simultaneously cause switching transients on chip, a problem associated with large pinout VLSI N/CMOS and bipolar devices during chip testing. By inhibiting OCD switching during functional testing, transient switching problems are eliminated. Through the utilization of a comparator circuit on all OCDs, as shown in the figure, only forced data from a tester is used to functionally test a chip. Each OCD is disabled through a control pin 10 which places OCD 11 into a high impedance state (tri-state) during a test. Normally, enable line 12 is utilized to condition OCD 11 to drive data line 13 off chip. To test data 13 coming from internal logic to disabled OCD 11 during the test mode, data is injected from the tester through a common off-chip driver/receiver (OCD/OCR) I/O pin 14. Gate line 15, coming from internal logic, normally gates OCR 16 but in the test mode gate line 15 is directed to exclusive OR (XOR) 19. Tp pin 17 is activated during test mode and becomes the other input to XOR 19. The output of XOR 19 is directed to multiplexer 20 and works in conjunction with data 13 when enable line 12 is inactive and gate line 15 is active. This allows testing of the logic driving the enable...