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New Approach to Level Sensitive Scan Design Testing

IP.com Disclosure Number: IPCOM000040647D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Bula, O: AUTHOR [+2]

Abstract

Level sensitive scan design (LSSD) semiconductor chips equipped with some additional scan path monitoring circuitry will result in a reduction in test data and output pin requirements. A block diagram overview of the design utilized by the new test method is shown in the figure. Circuitry added to an LSSD chip design includes: a) "N" bit shift latches for data compression and a reset circuit. b) "N" bit compare circuit. c) "N" bit parity generator. d) "N" latch multiplexer for data, plus two additional latches, i.e., one for a parity compression bit and one for the comparator result bit. A reset circuit is also needed.

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New Approach to Level Sensitive Scan Design Testing

Level sensitive scan design (LSSD) semiconductor chips equipped with some additional scan path monitoring circuitry will result in a reduction in test data and output pin requirements. A block diagram overview of the design utilized by the new test method is shown in the figure. Circuitry added to an LSSD chip design includes: a) "N" bit shift latches for data compression and a reset circuit.

b) "N" bit compare circuit.

c) "N" bit parity generator.

d) "N" latch multiplexer for data, plus two additional

latches, i.e., one for a parity compression bit and one

for the comparator result bit. A reset circuit is also

needed. A linear feedback shift register (LFSR) is utilized to compress and accumulate a composite bit pattern from the data flow seen at the output of the scan latches of the chip under test. The output of the LFSR is fed to a compare circuit. A combinatorial logic compare circuit is used to compare the output data from the LFSR with a pre-calculated data pattern (signature) for the test loop/loops used in a particular product test. Signature data is scanned into a product chip in the usual manner and routed to the compare circuit.

The compare circuit has a single bit output which is used to set a latch in the output multiplexer. The parity bit generator is utilized to dynamically generate and compress parity from bits being shifted out of selected scan chains for each step in the scan sequence. The parity circuit has a single bit output which is used to set a latch in the output multiplexer. The multiplexer circuit is capable of selecting for output either the compressed output of the comparator, the compressed output of the parity generator or the output of one selected scan chain. The multiplexer output pin is strobed by a tester. OPERATION 1) Initially control data is loaded into the scan latches to reset the LFSR and set up the multiplexer by selecting the path to be fed to the output pin. 2) The product chip clock is pulsed active, selecting the multiplexer and resetting the signature a...