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High Density Cross Point Semiconductor Memory Cell

IP.com Disclosure Number: IPCOM000040651D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Scheuerlein, RE: AUTHOR

Abstract

A high density cross point semiconductor cell which provides a large output signal for a small memory cell surface area is fabricated so as to maximize the signal storage capacity while minimizing the parasitic capacity. The figure shows a cross section of a high density cross point semiconductor memory cell featuring a buried signal storage trench 10 with a large circumference in order to maximize the trench storage node capacity Cs for maximum signal output. The structure has features at the wafer surface which occupy a much smaller area than the buried trench feature allowing closer cell-to-cell design spacing. A collar hole 11 from the top of the buried trench 10 to the wafer surface houses the cell's gate which is in contact with word line 12.

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High Density Cross Point Semiconductor Memory Cell

A high density cross point semiconductor cell which provides a large output signal for a small memory cell surface area is fabricated so as to maximize the signal storage capacity while minimizing the parasitic capacity. The figure shows a cross section of a high density cross point semiconductor memory cell featuring a buried signal storage trench 10 with a large circumference in order to maximize the trench storage node capacity Cs for maximum signal output. The structure has features at the wafer surface which occupy a much smaller area than the buried trench feature allowing closer cell-to-cell design spacing. A collar hole 11 from the top of the buried trench 10 to the wafer surface houses the cell's gate which is in contact with word line 12. It should be noted that the collar passes through a buried N+ diffused bit line 13 near the top of the collar. Bit line 13 passes by the cell orthogonal to word line 12 and bit line 13 passes around collar 11 (device gate) located directly above trench 10. The small collar hole allows for a reduced bit line width and pitch. Cell area shrinks in the direction of the word line because bit line spacing is no longer a constraint, resulting in reduced word line capacitance. These design factors help bring about a small cell size, reduce parasitic capacitance and maximize the storage node capacitance. A process overview for fabricating the high density cross point cell follows. After trench 10 is etched and insulator 15 is formed using conventional process tech...