Browse Prior Art Database

Asynchrone to Synchrone Converter

IP.com Disclosure Number: IPCOM000040657D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Fieschi, J: AUTHOR [+2]

Abstract

An asynchrone to synchrone converter is described having the capability to attach asynchronous DTE (Data Terminal Equipment) to a basic synchronous modem. The converter provides the modem with the transmitted data (xmit) in synchronism with a transmitted clock which is extracted from the START/STOP data signal coming from the DTE. The converter uses a simple implementation consisting of a data sampler 1 designed to send data into a data buffer 2 under the control of a write pointer PW and a PLO (Phase Loop Oscillator) 3. The converter allows transparency and achieves high data rates. Data Sampler 1 is a kind of START/STOP bit receiver as can usually be found in asynchronous DTE receivers.

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Asynchrone to Synchrone Converter

An asynchrone to synchrone converter is described having the capability to attach asynchronous DTE (Data Terminal Equipment) to a basic synchronous modem. The converter provides the modem with the transmitted data (xmit) in synchronism with a transmitted clock which is extracted from the START/STOP data signal coming from the DTE. The converter uses a simple implementation consisting of a data sampler 1 designed to send data into a data buffer 2 under the control of a write pointer PW and a PLO (Phase Loop Oscillator) 3. The converter allows transparency and achieves high data rates. Data Sampler 1 is a kind of START/STOP bit receiver as can usually be found in asynchronous DTE receivers. Basically, a free-running 4-bit counter is incremented by a local clock which is 16F where F is the nominal bit frequency for the asynchrone attachment. This counter is reset each time a transition is detected on the Xmit Data from the DTE 4. Each time the counter reaches the "8" count position, the Xmit data lead is sampled and the data bit is sent into the data buffer. When the counter is at the "F" position, it is reset at the next clock pulse by overflow. If there is no change in the following Xmit Data bit, the C counter will keep a sampling position based on the last received transition. It is important to note that the S/S protocol systematically assures transitions with the start and stop bits, whatever the data bits are. Data buffer 2 is an 8xl bit buffer. The Data bits from the sampler are sent into the Data buffer in consecutive positions under the control of a 3-bit Write Pointer (PW). The Write Pointer PW is incremented each time a data bit from the sampler is stored in the D...