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Address Key Register Table Extension for 16-Bit Level Status Block Computers

IP.com Disclosure Number: IPCOM000040670D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Bourke, DG: AUTHOR [+4]

Abstract

A technique is described whereby a table, which outlines an extended form of addressing context information, is added to an existing hardware context information control block of a computer processor. This technique extends and allows optimization of the management of the addressing capabilities of programs to be executed. The address key register (AKR) table is added as an extension to the level status block (LSB) by utilizing an address space key value and address pointer to the AKR table maintained in main storage of the computer. The currently active AKR index numbers and permanent AKR index numbers are kept in the extended LSB to reflect the processor context information required for setting the correct AKR values from the AKR table when resuming a preempted LSB.

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Address Key Register Table Extension for 16-Bit Level Status Block Computers

A technique is described whereby a table, which outlines an extended form of addressing context information, is added to an existing hardware context information control block of a computer processor. This technique extends and allows optimization of the management of the addressing capabilities of programs to be executed. The address key register (AKR) table is added as an extension to the level status block (LSB) by utilizing an address space key value and address pointer to the AKR table maintained in main storage of the computer. The currently active AKR index numbers and permanent AKR index numbers are kept in the extended LSB to reflect the processor context information required for setting the correct AKR values from the AKR table when resuming a preempted LSB. The AKR table is never written to main storage by the processor on a level switch or copy level block (CPLB) instruction, thereby reducing context information which would otherwise be saved. The concept described herein provides a means of synchronizing information concerning the AKR table entries contained inside of the processor and changes made by software to the AKR table in main storage. The processor with extended addressing will now have the ability to implement the AKR table using any of the following: 1) On context switch, the entire AKR table of the LSB being set can be read into internal high speed storage or registers. The synchronizing sub- functions of the Set AKR, From Address Key Table (SFAKT) instruction signal the processor that its internal copies of AKR table entries must be refreshed from the main storage AKR table. Howeve...